FPGA Development in VHDL - Beyond the Basics

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FPGA Development in VHDL - Beyond the Basics

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种子哈希：695e369f482d8bbfda78eacdc5fe9605e4ff2d28
文件大小：516.1M
已经下载：7730次
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收录时间：2017-07-06
最近下载：2026-06-10
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文件列表

  • 03.Working with Custom Data Types/09.Summary.srt 832 Bytes
  • 07.Testing Your Designs/05.Summary.srt 1.0 kB
  • 04.Monitoring Signal States with Attributes/01.Overview.srt 1.1 kB
  • 06.Constructing State Machines/07.Summary.srt 1.1 kB
  • 07.Testing Your Designs/01.Overview.srt 1.1 kB
  • 04.Monitoring Signal States with Attributes/06.Type Kind Attributes.srt 1.1 kB
  • 06.Constructing State Machines/03.State Machine Types.srt 1.2 kB
  • 03.Working with Custom Data Types/01.Overview.srt 1.3 kB
  • 04.Monitoring Signal States with Attributes/02.What Are Attributes.srt 1.4 kB
  • 06.Constructing State Machines/01.Overview.srt 1.4 kB
  • 05.Keeping Code Organized with Subprograms and Packages/07.Summary.srt 1.4 kB
  • 02.Developing for the FPGA/02.Module Overview.srt 1.5 kB
  • 03.Working with Custom Data Types/04.Subtypes.srt 1.5 kB
  • 05.Keeping Code Organized with Subprograms and Packages/01.Overview.srt 1.5 kB
  • 02.Developing for the FPGA/08.Summary.srt 1.5 kB
  • 04.Monitoring Signal States with Attributes/08.Summary.srt 1.7 kB
  • 03.Working with Custom Data Types/05.Multidimensional Arrays.srt 1.8 kB
  • 01.Course Overview/01.Course Overview.srt 2.0 kB
  • 06.Constructing State Machines/02.What Is a State Machine.srt 2.2 kB
  • 03.Working with Custom Data Types/06.Record Types.srt 2.6 kB
  • 04.Monitoring Signal States with Attributes/05.Signal Kind Attributes.srt 2.7 kB
  • 03.Working with Custom Data Types/07.Physical Types.srt 3.1 kB
  • 02.Developing for the FPGA/06.High-level Synthesis.srt 3.2 kB
  • 05.Keeping Code Organized with Subprograms and Packages/02.Design Unit Recap.srt 3.2 kB
  • 02.Developing for the FPGA/01.Course Overview.srt 3.4 kB
  • 04.Monitoring Signal States with Attributes/07.User-defined Attributes.srt 3.5 kB
  • 05.Keeping Code Organized with Subprograms and Packages/04.Constants.srt 3.8 kB
  • 02.Developing for the FPGA/03.VHDL Design Flow.srt 3.8 kB
  • 02.Developing for the FPGA/04.Compilation Process.srt 4.3 kB
  • 03.Working with Custom Data Types/02.Standard Data Types Recap.srt 5.2 kB
  • 04.Monitoring Signal States with Attributes/03.Value Kind Attributes.srt 5.5 kB
  • 03.Working with Custom Data Types/03.Arrays and Ranges.srt 6.9 kB
  • 07.Testing Your Designs/02.Testing and Testbenches.srt 7.0 kB
  • 05.Keeping Code Organized with Subprograms and Packages/03.Procedures.srt 8.5 kB
  • 06.Constructing State Machines/06.State Encoding Styles.srt 8.8 kB
  • 02.Developing for the FPGA/07.Demo - MATLAB HDL Coder.srt 9.3 kB
  • 02.Developing for the FPGA/05.Demo - Compilation Report.srt 9.4 kB
  • 07.Testing Your Designs/03.A Sample Testbench.srt 10.0 kB
  • 06.Constructing State Machines/04.Demo - Traffic Lights (Moore).srt 11.0 kB
  • 04.Monitoring Signal States with Attributes/04.Function Kind Attributes.srt 11.3 kB
  • 07.Testing Your Designs/04.Testing with VUnit.srt 13.4 kB
  • 05.Keeping Code Organized with Subprograms and Packages/05.Generics.srt 13.5 kB
  • 05.Keeping Code Organized with Subprograms and Packages/06.Resolution Functions.srt 13.8 kB
  • 06.Constructing State Machines/05.Demo - Combination Lock (Mealy).srt 17.8 kB
  • 03.Working with Custom Data Types/08.Demo.srt 20.4 kB
  • fpga-vhdl-beyond-basics.zip 859.9 kB
  • 07.Testing Your Designs/01.Overview.mp4 1.1 MB
  • 04.Monitoring Signal States with Attributes/01.Overview.mp4 1.2 MB
  • 07.Testing Your Designs/05.Summary.mp4 1.2 MB
  • 03.Working with Custom Data Types/09.Summary.mp4 1.2 MB
  • 06.Constructing State Machines/03.State Machine Types.mp4 1.3 MB
  • 06.Constructing State Machines/01.Overview.mp4 1.4 MB
  • 03.Working with Custom Data Types/01.Overview.mp4 1.4 MB
  • 04.Monitoring Signal States with Attributes/02.What Are Attributes.mp4 1.4 MB
  • 05.Keeping Code Organized with Subprograms and Packages/01.Overview.mp4 1.5 MB
  • 04.Monitoring Signal States with Attributes/06.Type Kind Attributes.mp4 1.5 MB
  • 02.Developing for the FPGA/02.Module Overview.mp4 1.6 MB
  • 05.Keeping Code Organized with Subprograms and Packages/07.Summary.mp4 1.6 MB
  • 06.Constructing State Machines/07.Summary.mp4 1.9 MB
  • 02.Developing for the FPGA/08.Summary.mp4 2.0 MB
  • 03.Working with Custom Data Types/05.Multidimensional Arrays.mp4 2.3 MB
  • 03.Working with Custom Data Types/04.Subtypes.mp4 2.4 MB
  • 04.Monitoring Signal States with Attributes/08.Summary.mp4 2.6 MB
  • 06.Constructing State Machines/02.What Is a State Machine.mp4 2.8 MB
  • 03.Working with Custom Data Types/06.Record Types.mp4 3.2 MB
  • 02.Developing for the FPGA/01.Course Overview.mp4 3.6 MB
  • 02.Developing for the FPGA/03.VHDL Design Flow.mp4 3.6 MB
  • 01.Course Overview/01.Course Overview.mp4 3.8 MB
  • 04.Monitoring Signal States with Attributes/05.Signal Kind Attributes.mp4 4.0 MB
  • 03.Working with Custom Data Types/07.Physical Types.mp4 4.3 MB
  • 02.Developing for the FPGA/06.High-level Synthesis.mp4 4.4 MB
  • 05.Keeping Code Organized with Subprograms and Packages/02.Design Unit Recap.mp4 4.4 MB
  • 04.Monitoring Signal States with Attributes/07.User-defined Attributes.mp4 4.5 MB
  • 05.Keeping Code Organized with Subprograms and Packages/04.Constants.mp4 5.0 MB
  • 02.Developing for the FPGA/04.Compilation Process.mp4 5.6 MB
  • 03.Working with Custom Data Types/02.Standard Data Types Recap.mp4 6.5 MB
  • 04.Monitoring Signal States with Attributes/03.Value Kind Attributes.mp4 7.5 MB
  • 07.Testing Your Designs/02.Testing and Testbenches.mp4 8.1 MB
  • 03.Working with Custom Data Types/03.Arrays and Ranges.mp4 10.8 MB
  • 05.Keeping Code Organized with Subprograms and Packages/03.Procedures.mp4 10.9 MB
  • 06.Constructing State Machines/06.State Encoding Styles.mp4 13.9 MB
  • 04.Monitoring Signal States with Attributes/04.Function Kind Attributes.mp4 15.8 MB
  • 02.Developing for the FPGA/07.Demo - MATLAB HDL Coder.mp4 23.5 MB
  • 07.Testing Your Designs/03.A Sample Testbench.mp4 26.7 MB
  • 02.Developing for the FPGA/05.Demo - Compilation Report.mp4 26.8 MB
  • 07.Testing Your Designs/04.Testing with VUnit.mp4 30.8 MB
  • 06.Constructing State Machines/04.Demo - Traffic Lights (Moore).mp4 41.5 MB
  • 05.Keeping Code Organized with Subprograms and Packages/06.Resolution Functions.mp4 42.9 MB
  • 05.Keeping Code Organized with Subprograms and Packages/05.Generics.mp4 50.4 MB
  • 06.Constructing State Machines/05.Demo - Combination Lock (Mealy).mp4 62.8 MB
  • 03.Working with Custom Data Types/08.Demo.mp4 84.1 MB

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