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[ DevCourseWeb.com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide
磁力链接/BT种子名称
[ DevCourseWeb.com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide
磁力链接/BT种子简介
种子哈希：
83b579cf9f673e12f87245955a43c4a717394cf8
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937.96M
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收录时间：
2022-05-17
最近下载：
2024-11-16
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文件列表
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/005 Step 4 - Add Existing Custom IP.mp4
51.1 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/001 Project Design Flow Walkthrough.mp4
38.9 MB
~Get Your Files Here !/07 - Automating Vivado/001 TCL Script Introduction.mp4
32.6 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/005 Vivado Debugging Tools Introduction.mp4
32.1 MB
~Get Your Files Here !/10 - High Level Synthesis Tool/001 High Level Synthesis Tool Introduction.mp4
31.0 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/006 How to Use the Integrated Logic Analyzer (ILA) Core for Debugging.mp4
28.3 MB
~Get Your Files Here !/01 - Introduction/001 Welcome to the Course.mp4
26.3 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/007 How to Use the Virtual IO (VIO) Core for Debugging.mp4
24.5 MB
~Get Your Files Here !/01 - Introduction/003 Vivado Download and Installation.mp4
23.2 MB
~Get Your Files Here !/05 - IP Core Design Examples/002 Xilinx Memory Interface Generator (MIG) IP Core.mp4
22.9 MB
~Get Your Files Here !/01 - Introduction/002 Introduction to the Vivado Tool Suite.mp4
22.7 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/004 Create IP Cores from a Block Design.mp4
22.6 MB
~Get Your Files Here !/03 - Pin Planning Tool/001 IO Pin Planning Tool Introduction.mp4
22.0 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/008 Create an AXI IP Core Peripheral Step 3.mp4
22.0 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/003 Create IP Cores from a Specific Directory.mp4
21.2 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/003 Modifying the Simulation Waveform.mp4
20.9 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/006 Step 5 - Add Create Design Constraints.mp4
20.8 MB
~Get Your Files Here !/02 - Vivado Basics/008 Working with Block Designs in Vivado.mp4
19.8 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/007 Step 6 - Simulate and Verify Design.mp4
19.6 MB
~Get Your Files Here !/09 - Working with Soft Core Processors/002 Add AXI Peripherals to Your MicroBlaze Processor.mp4
19.1 MB
~Get Your Files Here !/03 - Pin Planning Tool/003 Create and Place IO Ports.mp4
16.8 MB
~Get Your Files Here !/09 - Working with Soft Core Processors/001 Creating Your First Softcore Processor Project.mp4
16.7 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/014 Managing a Custom IP Core Repository.mp4
15.5 MB
~Get Your Files Here !/03 - Pin Planning Tool/006 Generate Contraints File and Top Level HDL File.mp4
15.4 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/blk_mem_gen_v8_3/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
14.8 MB
~Get Your Files Here !/05 - IP Core Design Examples/001 Configure Internal FPGA Block RAM (BRAM).mp4
14.4 MB
~Get Your Files Here !/02 - Vivado Basics/005 Vivado Example Project.mp4
14.3 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/002 Simulating Your Designs in Vivado.mp4
13.9 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/012 Adding IP Cores to Your Repository.mp4
13.7 MB
~Get Your Files Here !/02 - Vivado Basics/007 Creating New Files.mp4
13.4 MB
~Get Your Files Here !/05 - IP Core Design Examples/004 Using Vivado's Connection Automation and Regerating Block Design Layouts.mp4
13.1 MB
~Get Your Files Here !/02 - Vivado Basics/003 Importing a Xilinx ISE Project Into Vivado.mp4
12.6 MB
~Get Your Files Here !/02 - Vivado Basics/009 Generating the FPGA Configuration File.mp4
12.3 MB
~Get Your Files Here !/06 - Working with Design Constraints/003 Creating Clock Constraints.mp4
11.9 MB
~Get Your Files Here !/07 - Automating Vivado/005 How to Create Your Own Custom TCL Scripts.mp4
11.7 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/004 Forcing Signal Values for Simulation.mp4
11.6 MB
~Get Your Files Here !/07 - Automating Vivado/004 Using TCL Scripts in Your Custom IP Core.mp4
11.3 MB
~Get Your Files Here !/07 - Automating Vivado/002 Build a Vivado Project Using TCL Scripts.mp4
11.0 MB
~Get Your Files Here !/03 - Pin Planning Tool/005 Report Simultaneous Switching Noise SSN.mp4
10.9 MB
~Get Your Files Here !/06 - Working with Design Constraints/002 Applying IO Constraints.mp4
10.6 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/009 Customizing IP Cores.mp4
10.5 MB
~Get Your Files Here !/13 - Conclusion/001 Conclusion.mp4
10.5 MB
~Get Your Files Here !/05 - IP Core Design Examples/003 Connecting Multiple AXI Peripherals to a Single Master.mp4
10.3 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/008 Step 7 - Generate the FPGA Configuration File.mp4
10.2 MB
~Get Your Files Here !/02 - Vivado Basics/006 Add Existing Files to a Project.mp4
10.1 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/009 Step 8 – Program your Board to Verify Functionality.mp4
9.7 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/006 Create an AXI IP Core Peripheral Step 1.mp4
9.5 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/002 Using IP Cores.mp4
9.4 MB
~Get Your Files Here !/02 - Vivado Basics/004 Create a Project From a Predefined Template.mp4
8.6 MB
~Get Your Files Here !/11 - Programming the FPGA/003 Loading the Configuration File on the FPGA.mp4
8.0 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/004 Step 3 - Create Project in Vivado.mp4
7.9 MB
~Get Your Files Here !/02 - Vivado Basics/002 Creating a New Project in Vivado.mp4
7.8 MB
~Get Your Files Here !/03 - Pin Planning Tool/002 Create an IO Pin Planning Project.mp4
7.6 MB
~Get Your Files Here !/02 - Vivado Basics/010 Programming Your Development Board.mp4
7.5 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/Simulation_Example_sim_behav.wdb
7.5 MB
~Get Your Files Here !/02 - Vivado Basics/001 Opening Vivado.mp4
7.1 MB
~Get Your Files Here !/02 - Vivado Basics/011 Documentation Navigator.mp4
6.8 MB
~Get Your Files Here !/03 - Pin Planning Tool/004 Perform a Design Rules Check.mp4
6.6 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/013 Adding a Custom IP Core Repository to a Vivado Project.mp4
6.5 MB
~Get Your Files Here !/07 - Automating Vivado/003 Populate a Block Design Using TCL Scripts.mp4
5.1 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xml
4.7 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd
2.2 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.bit
2.2 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_routed.dcp
1.4 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_placed.dcp
1.2 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_localparam_inc.v
954.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_opt.dcp
940.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx
749.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.dcp
594.8 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg/BASYS_7_seg_documentation.pdf
573.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/doc/BASYS_7_seg_documentation.pdf
573.6 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/doc/BASYS_7_seg_documentation.pdf
573.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xci
458.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/synth/design_1_ila_0_0.vhd
419.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_addsub_v12_0/hdl/c_addsub_v12_0_vh_rfs.vhd
392.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_addsub_v12_0/hdl/c_addsub_v12_0_vh_rfs.vhd
392.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt
360.7 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/002 Project-Requirements.pdf
346.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.pb
309.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/usage_statistics_webtalk.xml
309.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/ila_v6_0_syn_rfs.v
267.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/layout/hw_ila_1.layout
247.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
242.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/ip/46a4281943398b66/dbg_hub_CV.dcp
226.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_utils_v3_0_5/xbip_utils_v3_0_5_pkg.vdb
219.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.log
212.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.vds
211.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/usage_statistics_webtalk.html
202.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsimk.exe
191.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_xsdbm.v
176.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/xsdbm_v1_1_vl_rfs.v
170.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0_vh_rfs.vhd
159.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0_vh_rfs.vhd
159.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd
157.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd
157.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_param_inc.v
147.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
142.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
142.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_counter_v3_0/hdl/xbip_counter_v3_0_vh_rfs.vhd
130.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_counter_v3_0/hdl/xbip_counter_v3_0_vh_rfs.vhd
130.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0_vh_rfs.vhd
128.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0_vh_rfs.vhd
128.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/pkg_gate_bit_v12_0.vdb
122.9 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_isim_beh.exe
120.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0.vhd
91.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/ltlib_v1_0_vl_rfs.v
89.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
86.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
86.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.xml
78.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.sysdef
77.3 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.bit
72.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_base_legacy.vdb
72.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_lut6_legacy.vdb
71.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_pkg_legacy.vdb
70.4 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ibs
61.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_io_placed.rpt
61.5 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_par.xrpt
61.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_in_ports_inc.v
60.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_legacy.vdb
60.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_legacy.vdb
57.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_pkg.vdb
55.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_control_sets_placed.rpt
55.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_pkg.vdb
50.1 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/MouseCtl.vhd
48.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_pkg.vdb
44.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_viv.vdb
42.5 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/component.xml
40.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/component.xml
40.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_viv.vdb
38.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbs_v1_0/hdl/xsdbs_v1_0_vl_rfs.v
37.2 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/usage_statistics_webtalk.html
36.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48_wrapper_v3_0_4_pkg.vdb
35.1 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xise
33.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_viv.vdb
32.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0_vh_rfs.vhd
32.7 kB
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32.7 kB
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32.1 kB
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31.4 kB
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30.9 kB
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29.9 kB
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28.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd
27.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd
27.2 kB
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27.2 kB
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27.1 kB
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27.0 kB
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26.0 kB
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25.7 kB
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25.6 kB
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25.2 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/007 Creating an AXI IP Core Peripheral - Step 2.html
25.2 kB
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25.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd
24.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd
24.6 kB
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24.0 kB
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22.7 kB
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22.6 kB
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22.5 kB
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21.7 kB
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21.3 kB
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21.1 kB
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20.8 kB
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20.4 kB
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20.0 kB
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19.5 kB
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19.4 kB
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18.4 kB
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18.0 kB
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17.9 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0_S00_AXI.vhd
17.4 kB
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17.4 kB
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17.2 kB
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17.1 kB
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17.1 kB
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16.5 kB
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16.4 kB
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16.4 kB
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16.4 kB
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16.1 kB
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16.0 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/005 AXI Interface Explained.html
15.6 kB
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15.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xml
15.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.xml
15.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.xml
15.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.xml
15.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_viv.vdb
15.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xvhdl.pb
14.5 kB
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14.5 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/component.xml
14.5 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/vga_ctrl.vhd
14.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.mem
14.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_0/constraints/ila.xdc
14.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_fabric_legacy.vdb
14.0 kB
~Get Your Files Here !/02 - Vivado Basics/7_seg_project/7_seg.xdc
13.5 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/Basys3_Master.xdc
13.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/constrs_1/imports/XDC/Basys3_Master.xdc
13.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_synth.vdb
13.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_addsub_v12_0/hdl/c_addsub_v12_0.vhd
12.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_addsub_v12_0/hdl/c_addsub_v12_0.vhd
12.6 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.xrpt
12.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.xml
12.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.xml
12.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.xml
12.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.xml
12.5 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/binary_bcd/component.xml
12.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
12.2 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/component.xml
12.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_viv.vdb
12.0 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/MouseDisplay.vhd
11.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/006 How to Use the Integrated Logic Analyzer (ILA) Core for Debugging_en.srt
11.6 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_xst.xrpt
11.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_ver_inc.v
11.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0.vhd
11.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0.vhd
11.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.xci
10.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0.vhd
10.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0.vhd
10.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd
10.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd
10.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_utilization_placed.rpt
10.7 kB
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10.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/route_design.pb
10.7 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.xci
10.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_c_counter_binary_1_0/design_1_c_counter_binary_1_0.xci
10.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/usage_statistics_ext_labtool.html
10.5 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.syr
10.4 kB
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10.3 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/PWM/component.xml
10.2 kB
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10.2 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/src/basys_image.PNG
10.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/007 How to Use the Virtual IO (VIO) Core for Debugging_en.srt
9.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_counter_v3_0/hdl/xbip_counter_v3_0.vhd
9.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_counter_v3_0/hdl/xbip_counter_v3_0.vhd
9.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/compile.log
9.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xvhdl.log
9.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd
9.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd
9.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/003 Create IP Cores from a Specific Directory_en.srt
9.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/001 Introduction to IP Cores.html
9.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt
9.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/003 Modifying the Simulation Waveform_en.srt
9.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.type
9.2 kB
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9.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd
9.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.xpr
9.0 kB
~Get Your Files Here !/01 - Introduction/003 Vivado Download and Installation_en.srt
8.9 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/iseconfig/Full_Adder_2.projectmgr
8.9 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_summary.html
8.8 kB
~Get Your Files Here !/05 - IP Core Design Examples/002 Xilinx Memory Interface Generator (MIG) IP Core_en.srt
8.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.reloc
8.6 kB
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8.5 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/design.tcl
8.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8.vdb
8.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xelab.pb
8.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd
8.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd
8.3 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/008 Create an AXI IP Core Peripheral Step 3_en.srt
8.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/opt_design.pb
8.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/hw.xml
8.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.xdbg
8.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_lib_function.v
7.9 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/bd/bd.tcl
7.8 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/bd/bd.tcl
7.8 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/004 Create IP Cores from a Block Design_en.srt
7.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper_utilization_synth.rpt
7.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/verilog/ltlib_v1_0_0_lib_function.v
7.7 kB
~Get Your Files Here !/02 - Vivado Basics/008 Working with Block Designs in Vivado_en.srt
7.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1.vdb
7.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_1_inc.v
7.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbs_v1_0/hdl/verilog/xsdbs_v1_0_2_inc.v
7.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_c_counter_binary_0_0.vdb
7.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/verilog/ltlib_v1_0_0_ver_inc.v
7.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8.vdb
7.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hdl/design_1.vhd
7.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1.vdb
7.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/ISEWrap.js
7.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/ISEWrap.js
7.3 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/clk_wiz_0_clk_wiz.vhd
7.2 kB
~Get Your Files Here !/09 - Working with Soft Core Processors/001 Creating Your First Softcore Processor Project_en.srt
7.1 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/BASYS_7_seg_AXI_v1_0_tb.v
7.0 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/BASYS_7_seg_AXI_v1_0_tb.v
7.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/hdl/design_1.vhd
7.0 kB
~Get Your Files Here !/09 - Working with Soft Core Processors/002 Add AXI Peripherals to Your MicroBlaze Processor_en.srt
6.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/001 Creating Simulation Files (Test Benches).html
6.9 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/007 Step 6 - Simulate and Verify Design_en.srt
6.9 kB
~Get Your Files Here !/07 - Automating Vivado/design_1_tcl/design_1.tcl
6.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/usage_statistics_ext_labtool.html
6.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/imports/Hex_to_7_Seg/component.xml
6.6 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/Hex_to_7_Seg/component.xml
6.6 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/006 Step 5 - Add Create Design Constraints_en.srt
6.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/design_1.bxml
6.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_hdl_comps.vdb
6.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/gen_run.xml
6.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/write_bitstream.pb
6.3 kB
~Get Your Files Here !/02 - Vivado Basics/005 Vivado Example Project_en.srt
6.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/synth/design_1_c_counter_binary_0_0.vhd
6.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/ip/46a4281943398b66/46a4281943398b66.xci
6.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/usage_statistics_ext_labtool.xml
6.2 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/planAhead.log
6.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1.vdb
6.2 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_pad.csv
6.1 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.pad
6.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_1_icon2xsdb_inc.v
6.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbs_v1_0/hdl/verilog/xsdbs_v1_0_2_icon2xsdb_inc.v
6.0 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_usage.xml
6.0 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.mrp
5.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_viv_comp.vdb
5.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_comp.vdb
5.8 kB
~Get Your Files Here !/03 - Pin Planning Tool/003 Create and Place IO Ports_en.srt
5.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_viv_comp.vdb
5.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/014 Managing a Custom IP Core Repository_en.srt
5.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_comp.vdb
5.6 kB
~Get Your Files Here !/03 - Pin Planning Tool/006 Generate Contraints File and Top Level HDL File_en.srt
5.6 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_ngdbuild.xrpt
5.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1.vdb
5.5 kB
~Get Your Files Here !/05 - IP Core Design Examples/001 Configure Internal FPGA Block RAM (BRAM)_en.srt
5.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/basys_7_seg.vdb
5.4 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.par
5.4 kB
~Get Your Files Here !/02 - Vivado Basics/007 Creating New Files_en.srt
5.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1.vdb
5.3 kB
~Get Your Files Here !/01 - Introduction/004 Supported FPGAs and Development Boards.html
5.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_c_counter_binary_0_0/sim/design_1_c_counter_binary_0_0.vhd
5.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/sim/design_1_c_counter_binary_0_0.vhd
5.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_basys_7_seg_0_0.vdb
5.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_tier.vdb
5.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_1_icon_inc.v
5.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1.vdb
5.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/doc/c_counter_binary_v12_0_changelog.txt
5.0 kB
~Get Your Files Here !/02 - Vivado Basics/009 Generating the FPGA Configuration File_en.srt
5.0 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/001 Project Design Flow Walkthrough_en.srt
4.9 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.bgn
4.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/004 Forcing Signal Values for Simulation_en.srt
4.9 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/planAhead.log
4.8 kB
~Get Your Files Here !/02 - Vivado Basics/003 Importing a Xilinx ISE Project Into Vivado_en.srt
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/elaborate.log
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_viv_comp.vdb
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/002 Simulating Your Designs in Vivado_en.srt
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_comp.vdb
4.8 kB
~Get Your Files Here !/07 - Automating Vivado/005 How to Create Your Own Custom TCL Scripts_en.srt
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.xci
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.xci
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.xci
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.xci
4.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/synth/design_1_BASYS_7_seg_0_0.vhd
4.7 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.ngm
4.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_viv_comp.vdb
4.6 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/UART_TX_CTRL.vhd
4.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_comp.vdb
4.6 kB
~Get Your Files Here !/03 - Pin Planning Tool/005 Report Simultaneous Switching Noise SSN_en.srt
4.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/Simulation_Example_sim_vhdl.prj
4.5 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/012 Adding IP Cores to Your Repository_en.srt
4.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/doc/ila_v6_0_changelog.txt
4.4 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0.vhd
4.4 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0.vhd
4.4 kB
~Get Your Files Here !/05 - IP Core Design Examples/004 Using Vivado's Connection Automation and Regerating Block Design Layouts_en.srt
4.4 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1.hwdef
4.4 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/clk_wiz_0.vhd
4.3 kB
~Get Your Files Here !/07 - Automating Vivado/002 Build a Vivado Project Using TCL Scripts_en.srt
4.2 kB
~Get Your Files Here !/07 - Automating Vivado/001 TCL Script Introduction_en.srt
4.2 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/009 Step 8 – Program your Board to Verify Functionality_en.srt
4.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_routed.rpt
4.2 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/xgui/BASYS_7_seg_AXI_v1_0.tcl
4.1 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/xgui/BASYS_7_seg_AXI_v1_0.tcl
4.1 kB
~Get Your Files Here !/06 - Working with Design Constraints/003 Creating Clock Constraints_en.srt
4.1 kB
~Get Your Files Here !/07 - Automating Vivado/004 Using TCL Scripts in Your Custom IP Core_en.srt
4.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_BASYS_7_seg_0_0/sim/design_1_BASYS_7_seg_0_0.vhd
4.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/sim/design_1_BASYS_7_seg_0_0.vhd
4.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_viv_comp.vdb
4.0 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/002 Using IP Cores_en.srt
4.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_comp.vdb
4.0 kB
~Get Your Files Here !/02 - Vivado Basics/001 Opening Vivado_en.srt
4.0 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/design.tcl
3.9 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/design.tcl
3.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/project.wdf
3.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/project.wdf
3.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.vhd
3.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/synth/design_1_xlslice_1_0.vhd
3.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/synth/design_1_xlslice_2_0.vhd
3.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/synth/design_1_xlslice_3_0.vhd
3.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/simulation_example_sim.vdb
3.8 kB
~Get Your Files Here !/02 - Vivado Basics/006 Add Existing Files to a Project_en.srt
3.8 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/create_project.tcl
3.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1_viv_comp.vdb
3.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/synthesis.wdf
3.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1_comp.vdb
3.8 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_isim_beh.wdb
3.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/synth/design_1_Hex_to_7_Seg_0_0.vhd
3.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/synth/design_1_Hex_to_7_Seg_1_0.vhd
3.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/synth/design_1_Hex_to_7_Seg_2_0.vhd
3.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/synth/design_1_Hex_to_7_Seg_3_0.vhd
3.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/005 Vivado Debugging Tools Introduction_en.srt
3.7 kB
~Get Your Files Here !/10 - High Level Synthesis Tool/001 High Level Synthesis Tool Introduction_en.srt
3.7 kB
~Get Your Files Here !/06 - Working with Design Constraints/002 Applying IO Constraints_en.srt
3.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.vho
3.6 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/008 Step 7 - Generate the FPGA Configuration File_en.srt
3.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_viv_comp.vdb
3.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg/BASYS_7_seg.vhd
3.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/src/BASYS_7_seg.vhd
3.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/BASYS_7_seg.vhd
3.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/src/BASYS_7_seg.vhd
3.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ipshared/xilinx.com/basys_7_seg_v1_0/BASYS_7_seg.vhd
3.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/basys_7_seg_v1_0/BASYS_7_seg.vhd
3.6 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/BASYS_7_seg.vhd
3.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_comp.vdb
3.5 kB
~Get Your Files Here !/11 - Programming the FPGA/003 Loading the Configuration File on the FPGA_en.srt
3.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_wrapper.vdb
3.4 kB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/debouncer.vhd
3.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.xci
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.xci
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.xci
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.xci
3.3 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/binary_bcd/binary_bcd.vhd
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.veo
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/hex_to_7_seg.vdb
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_viv_comp.vdb
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.vho
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/webtalk/usage_statistics_ext_xsim.html
3.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_comp.vdb
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.vhd
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/sim/design_1_xlslice_0_0.vhd
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_1_0/sim/design_1_xlslice_1_0.vhd
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/sim/design_1_xlslice_1_0.vhd
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_2_0/sim/design_1_xlslice_2_0.vhd
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_xlslice_3_0/sim/design_1_xlslice_3_0.vhd
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/sim/design_1_xlslice_2_0.vhd
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/sim/design_1_xlslice_3_0.vhd
3.2 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/webtalk_pn.xml
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.vho
3.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.vho
3.2 kB
~Get Your Files Here !/05 - IP Core Design Examples/003 Connecting Multiple AXI Peripherals to a Single Master_en.srt
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/sim/design_1_Hex_to_7_Seg_0_0.vhd
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/sim/design_1_Hex_to_7_Seg_1_0.vhd
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/sim/design_1_Hex_to_7_Seg_2_0.vhd
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/sim/design_1_Hex_to_7_Seg_3_0.vhd
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/sim/design_1_Hex_to_7_Seg_0_0.vhd
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/sim/design_1_Hex_to_7_Seg_1_0.vhd
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/sim/design_1_Hex_to_7_Seg_2_0.vhd
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/sim/design_1_Hex_to_7_Seg_3_0.vhd
3.1 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/006 Create an AXI IP Core Peripheral Step 1_en.srt
3.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.veo
3.0 kB
~Get Your Files Here !/01 - Introduction/001 Welcome to the Course_en.srt
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/dont_touch.xdc
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.veo
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.veo
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.veo
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.veo
3.0 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ncd
3.0 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_guide.ncd
3.0 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/009 Customizing IP Cores_en.srt
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.veo
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/design_1_xlslice_1_0.veo
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.veo
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.veo
3.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/Xil/design_1_wrapper_propImpl.xdc
2.9 kB
~Get Your Files Here !/02 - Vivado Basics/010 Programming Your Development Board_en.srt
2.9 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/sub00/vhpl01.vho
2.9 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/013 Adding a Custom IP Core Repository to a Vivado Project_en.srt
2.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/gen_run.xml
2.9 kB
~Get Your Files Here !/02 - Vivado Basics/004 Create a Project From a Predefined Template_en.srt
2.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/webtalk/usage_statistics_ext_xsim.xml
2.8 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/test_Full_Adder_2.vhd
2.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_0_0.vdb
2.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_1_0.vdb
2.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_2_0.vdb
2.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_xlslice_3_0.vdb
2.8 kB
~Get Your Files Here !/02 - Vivado Basics/002 Creating a New Project in Vivado_en.srt
2.8 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.tcl
2.7 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.map
2.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/debug_nets.ltx
2.7 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.h
2.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.h
2.6 kB
~Get Your Files Here !/03 - Pin Planning Tool/001 IO Pin Planning Tool Introduction_en.srt
2.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.vhd
2.6 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.twr
2.6 kB
~Get Your Files Here !/03 - Pin Planning Tool/002 Create an IO Pin Planning Project_en.srt
2.6 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/004 Step 3 - Create Project in Vivado_en.srt
2.6 kB
~Get Your Files Here !/02 - Vivado Basics/7_seg_project/Hex_to_7_Seg_top.vhd
2.6 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ngd
2.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0_ooc.xdc
2.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0_ooc.xdc
2.5 kB
~Get Your Files Here !/02 - Vivado Basics/011 Documentation Navigator_en.srt
2.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_0_0.vdb
2.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_1_0.vdb
2.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_2_0.vdb
2.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_hex_to_7_seg_3_0.vdb
2.4 kB
~Get Your Files Here !/01 - Introduction/002 Introduction to the Vivado Tool Suite_en.srt
2.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_utils_v3_0_5/xcc_utils_v3_0.vdb
2.3 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.ncd
2.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/init_design.pb
2.3 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1.vhd
2.2 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/PWM/xgui/PWM_v1_0.tcl
2.1 kB
~Get Your Files Here !/06 - Working with Design Constraints/001 What are Design Constraints.html
2.1 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI_selftest.c
2.0 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI_selftest.c
2.0 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xdl
2.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.tcl
1.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
1.9 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/xlslice.vdb
1.9 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/003 Step 2 - Select FPGA Based on Requirements.html
1.9 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/Final_Project_Test_Bench.vhd
1.8 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/PWM/PWM.vhd
1.8 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/planAhead.jou
1.8 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/002 Step 1 - Acquire Project Requirements.html
1.8 kB
~Get Your Files Here !/03 - Pin Planning Tool/004 Perform a Design Rules Check_en.srt
1.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sim_1/imports/Lecture_Example/Simulation_Example_sim.vhd
1.7 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_opted.rpt
1.6 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/xgui/BASYS_7_seg_v1_0.tcl
1.6 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/xgui/BASYS_7_seg_v1_0.tcl
1.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/ISEWrap.sh
1.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/ISEWrap.sh
1.6 kB
~Get Your Files Here !/11 - Programming the FPGA/002 Prior to Programming Checklist.html
1.6 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/trce.xmsgs
1.6 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/webtalk_pa.xml
1.5 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/planAhead.jou
1.5 kB
~Get Your Files Here !/07 - Automating Vivado/003 Populate a Block Design Using TCL Scripts_en.srt
1.5 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
1.5 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/wt/webtalk_pa.xml
1.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wcfg
1.4 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/BASYS_7_seg_AXI_v1_0_hw_test.tcl
1.4 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/BASYS_7_seg_AXI_v1_0_hw_test.tcl
1.4 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/wt/webtalk_pa.xml
1.4 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/rundef.js
1.4 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ngc
1.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/rundef.js
1.3 kB
~Get Your Files Here !/11 - Programming the FPGA/001 Vivado Hardware Manager Introduction.html
1.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/runme.sh
1.3 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ipshared/xilinx.com/xlslice_v1_0/xlslice.vhd
1.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xlslice_v1_0/xlslice.vhd
1.2 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.sh
1.2 kB
~Get Your Files Here !/13 - Conclusion/001 Conclusion_en.srt
1.2 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ngr
1.2 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xst
1.2 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/010 Creating a Custom IP Core Repository.html
1.1 kB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/011 IP Core Repository Directory Structure.html
1.1 kB
~Get Your Files Here !/02 - Vivado Basics/7_seg_project/Hex_to_7_Seg.vhd
1.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ipshared/xilinx.com/hex_to_7_seg_v1_0/Hex_to_7_Seg.vhd
1.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/hex_to_7_seg_v1_0/Hex_to_7_Seg.vhd
1.1 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/imports/Hex_to_7_Seg/Hex_to_7_Seg.vhd
1.1 kB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/Hex_to_7_Seg/Hex_to_7_Seg.vhd
1.1 kB
~Get Your Files Here !/05 - IP Core Design Examples/BRAM_Init_File/memory_init.coe
1.1 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.bld
1.1 kB
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1.1 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/planAhead_run.log
1.1 kB
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1.0 kB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pa.fromNcd.tcl
1.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/webtalk_19988.backup.log
1.0 kB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/webtalk.log
1.0 kB
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971 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/webtalk_19988.backup.jou
944 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/webtalk.jou
943 Bytes
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792 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/pn_parser.xmsgs
778 Bytes
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777 Bytes
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769 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado_10904.backup.jou
769 Bytes
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769 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado_20632.backup.jou
769 Bytes
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764 Bytes
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741 Bytes
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726 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/webtalk.log
697 Bytes
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684 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_power_summary_routed.pb
674 Bytes
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/_READ_ME_.txt
670 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_route_status.rpt
651 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pa.fromHdl.tcl
646 Bytes
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645 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/xst.xmsgs
625 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/elaborate.bat
615 Bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_ooc.xdc
600 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/design_1_ooc.xdc
600 Bytes
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589 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/fileset.xml
589 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/constrs_1/fileset.xml
561 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/sources_1/fileset.xml
547 Bytes
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/cleanup.sh
533 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/xdl.xmsgs
512 Bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/Makefile
484 Bytes
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484 Bytes
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467 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/external-assets-links.txt
464 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/Simulation_Example_sim.tcl
458 Bytes
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/cleanup.cmd
453 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.pcf
451 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/hdpdeps.ref
423 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/java_command_handlers.wdf
417 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead.ngc2edif.log
413 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_summary.xml
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406 Bytes
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401 Bytes
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~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ut
392 Bytes
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391 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/labtool_webtalk.log
386 Bytes
~Get Your Files Here !/Bonus Resources.txt
386 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/bitgen.xmsgs
367 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/ngdbuild.xmsgs
367 Bytes
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365 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/constrs_1/fileset.xml
361 Bytes
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360 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado.begin.rst
352 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/compile.bat
345 Bytes
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343 Bytes
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324 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/simulate.bat
321 Bytes
~Get Your Files Here !/06 - Working with Design Constraints/external-assets-links.txt
313 Bytes
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306 Bytes
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277 Bytes
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256 Bytes
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_utilization_placed.pb
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230 Bytes
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229 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.bat
229 Bytes
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210 Bytes
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210 Bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/xgui/design_1_v1_0.tcl
205 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/imports/Hex_to_7_Seg/xgui/Hex_to_7_Seg_v1_0.tcl
205 Bytes
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205 Bytes
~Get Your Files Here !/01 - Introduction/external-assets-links.txt
197 Bytes
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197 Bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.c
194 Bytes
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194 Bytes
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190 Bytes
Get Bonus Downloads Here.url
182 Bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.tcl
177 Bytes
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177 Bytes
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177 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/init_design.begin.rst
177 Bytes
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177 Bytes
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177 Bytes
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177 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.begin.rst
175 Bytes
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156 Bytes
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153 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado.pb
149 Bytes
~Get Your Files Here !/03 - Pin Planning Tool/external-assets-links.txt
143 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/README.txt
130 Bytes
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121 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/chipscope.xml
113 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/synthesis_details.wdf
100 Bytes
~Get Your Files Here !/05 - IP Core Design Examples/external-assets-links.txt
95 Bytes
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84 Bytes
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81 Bytes
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78 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/test_Full_Adder_2_stx_beh.prj
75 Bytes
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65 Bytes
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64 Bytes
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59 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/xsim_webtallk.info
59 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/simulate.log
50 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xpi
46 Bytes
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44 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_route_status.pb
44 Bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_routed.pb
37 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_stx_beh.prj
35 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.prj
30 Bytes
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29 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pepExtractor.prj
25 Bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xilinxsim.ini
16 Bytes
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8 Bytes
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6 Bytes
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0 Bytes
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0 Bytes
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/init_design.end.rst
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/opt_design.end.rst
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/route_design.end.rst
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado.end.rst
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/write_bitstream.end.rst
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/Vivado_Synthesis.queue.rst
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