[ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming

磁力链接/BT种子名称

[ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming

磁力链接/BT种子简介

种子哈希：b7e4717fb5c9d11777af7048498f5ca4da56a4ec
文件大小： 1.33G
已经下载：1517次
下载速度：极快
收录时间：2024-01-13
最近下载：2024-11-16

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文件列表

  • ~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench.mp4 557.2 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench.mp4 342.1 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB.mp4 263.6 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator.mp4 97.7 MB
  • ~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART.mp4 31.3 MB
  • ~Get Your Files Here !/01 - Introduction/001 Preview.mp4 28.4 MB
  • ~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication.mp4 25.4 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment.mp4 23.2 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator.mp4 12.3 MB
  • ~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART.mp4 10.9 MB
  • ~Get Your Files Here !/02 - Introduction to UART/001 What is UART.mp4 7.2 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter.mp4 7.0 MB
  • ~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication.mp4 6.5 MB
  • ~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication.mp4 6.1 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver.mp4 5.8 MB
  • ~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART.mp4 3.5 MB
  • ~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt 46.7 kB
  • ~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt 28.9 kB
  • ~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt 26.5 kB
  • ~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator_en.vtt 10.5 kB
  • ~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART_en.vtt 4.9 kB
  • ~Get Your Files Here !/01 - Introduction/001 Preview_en.vtt 4.7 kB
  • ~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment_en.vtt 3.6 kB
  • ~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART_en.vtt 2.8 kB
  • ~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication_en.vtt 2.8 kB
  • ~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator_en.vtt 2.1 kB
  • ~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter_en.vtt 1.4 kB
  • ~Get Your Files Here !/02 - Introduction to UART/001 What is UART_en.vtt 1.4 kB
  • ~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver_en.vtt 1.2 kB
  • ~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication_en.vtt 1.1 kB
  • ~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication_en.vtt 970 Bytes
  • ~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART_en.vtt 632 Bytes
  • ~Get Your Files Here !/Bonus Resources.txt 386 Bytes
  • Get Bonus Downloads Here.url 180 Bytes

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