Analog Digital ASICs design_Part II

磁力链接/BT种子名称

Analog Digital ASICs design_Part II

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收录时间：2017-03-18
最近下载：2024-11-11

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文件列表

  • Articles about Design Verification Techniques/A Case Study of Verification with Embedded Checkers.pdf 309.7 kB
  • Articles about Design Verification Techniques/A Recipe for Multi-Million Gate ASIC Verification.pdf 71.4 kB
  • Articles about Design Verification Techniques/A Strategic Process for System Level Verification.pdf 577.6 kB
  • Articles about Design Verification Techniques/Assertion Monitor Library_100.pdf 157.8 kB
  • Articles about Design Verification Techniques/Component Verification by Example.pdf 164.3 kB
  • Articles about Design Verification Techniques/Design and Verification IP for PCI and PCI-X.pdf 332.2 kB
  • Articles about Design Verification Techniques/Exploiting the Power of Vera--Creating Useful Class Librarie.pdf 108.4 kB
  • Articles about Design Verification Techniques/Functional Verification of a HW Block Using VERA.pdf 72.7 kB
  • Articles about Design Verification Techniques/Functional Verification with Embedded Checkers --Paper.pdf 181.2 kB
  • Articles about Design Verification Techniques/Getting It Right--AMS Design and Verification Strategies.pdf 234.3 kB
  • Articles about Design Verification Techniques/High Level Data Structures in Verification and Behavioral Mo.pdf 1.1 MB
  • Articles about Design Verification Techniques/Portable Automatic In-Situ Testbench Generation-- A Case Stu.pdf 144.0 kB
  • Articles about Design Verification Techniques/practical_soc_verification.pdf 103.3 kB
  • Articles about Design Verification Techniques/Random Generation Tutorial.pdf 1.6 MB
  • Articles about Design Verification Techniques/Shotgun E An Eight-Step Approach to Experience Random Verifi.pdf 136.9 kB
  • Articles about Design Verification Techniques/Spec-Based Verification.pdf 132.7 kB
  • Articles about Design Verification Techniques/The Case for eVCs.pdf 127.6 kB
  • Articles about Design Verification Techniques/The Five-Day Verification Plan.pdf 74.9 kB
  • Articles about Design Verification Techniques/Using VCS with White-Box Verification Techniques --Paper.pdf 37.4 kB
  • Articles about Design Verification Techniques/Using VERA to Test a DMA Engine.pdf 42.2 kB
  • Articles about Design Verification Techniques/Vera, Vera On the Wall, Useful Lessons for First-Time Vera U.pdf 83.6 kB
  • Articles about Design Verification Techniques/Verification Methodology of Multi-Million Gate Networking So.pdf 48.8 kB
  • Articles about Design Verification Techniques/Verifying Virtual Components and VC-Based SoC Designs --pape.pdf 318.7 kB
  • Articles about Design Verification Techniques/When Test Vectors are Useless -- Verifying IP-Based SOC Desi.pdf 551.4 kB
  • Articles about Design Verification Techniques/White-Box Verification for Complex Designs.pdf 98.0 kB
  • CMOS Circuit Design, Layout, and Simulation.R.Jacob Baker, Harry W.Li, David E.Boyce.pdf 157.2 MB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixa.pdf 294.8 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixb.pdf 528.9 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixc.pdf 258.1 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixd.pdf 382.2 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixe.pdf 189.6 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixf.pdf 269.0 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch0.pdf 177.1 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch1.pdf 704.6 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch10.pdf 1.5 MB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch11.pdf 1.1 MB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch12.pdf 1.4 MB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch13.pdf 806.6 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch14.pdf 1.6 MB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch15.pdf 343.6 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch16.pdf 149.6 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch2.pdf 700.8 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch3.pdf 870.2 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch4.pdf 781.1 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch5.pdf 1.2 MB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch6.pdf 987.6 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch7.pdf 826.5 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch8.pdf 652.1 kB
  • Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch9.pdf 448.6 kB
  • Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds1.pdf 4.5 MB
  • Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds2.pdf 4.3 MB
  • Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds3.pdf 4.5 MB
  • Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds4.pdf 4.2 MB
  • Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds5.pdf 4.2 MB
  • Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds6.pdf 4.6 MB
  • Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds7.pdf 4.6 MB
  • Design of Analog CMOS Integrated Cirquits.Behzad Razavi/cmos errata.pdf 19.6 kB
  • Design of Analog CMOS Integrated Cirquits.Behzad Razavi/Design of Analog CMOS Integrated Circuits.pdf 18.2 MB
  • Design of analog Integrated Cirquits and Systems.Kenneth.R.Laker,Willy.M.C.Sansen.pdf 213.9 MB
  • Design of Low-voltage Low-Power CMOS Delta-Sigma AD Converters.Vincento Peluso,Michel Steyaert,Willy Sansen.pdf 19.9 MB
  • Design of Low-Voltage Low-Power Operational Amplifiers Cells.Ron Hogervorst,Johan H.Huijsing.pdf 35.5 MB
  • Design of System on a Chip.Devices & Components.Ricardo Reis, Jochen A.G. Jess.pdf 7.4 MB
  • Designing Analog Chips.Hans Camenzind.pdf 2.0 MB
  • Designing with Operational amplifiers.Applications Alternatives.Jerald G.Graeme.pdf 9.6 MB
  • ECE422_ECE522 CMOS IC Technologies Lectures. Karti Mayaram/hand-all.pdf 7.9 MB
  • ECE422_ECE522 CMOS IC Technologies Lectures. Karti Mayaram/part1.pdf 1.1 MB
  • ECE422_ECE522 CMOS IC Technologies Lectures. Karti Mayaram/part2.pdf 742.5 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_01.pdf 1.5 MB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_02.pdf 484.5 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_03.pdf 546.4 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_04.pdf 325.9 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_05.pdf 388.9 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_06.pdf 475.6 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_07.pdf 565.1 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_08.pdf 604.5 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_09.pdf 415.6 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_10.pdf 440.7 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_11.pdf 1.3 MB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_12.pdf 1.4 MB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_13.pdf 610.6 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_14.pdf 854.8 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_15.pdf 791.5 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_16.pdf 602.5 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_17.pdf 545.6 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_18.pdf 1.2 MB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_19.pdf 608.8 kB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_20.pdf 1.9 MB
  • EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_21.pdf 881.0 kB
  • From ASIC to SOCs.A practical Approach.Farzad Nekoogar, Faranak Nekoogar.chm 2.0 MB
  • High Speed CMOS Design Styles. 7 Autors from IBM.pdf 125.8 MB
  • IC Layout Basics.A Practical Guide.Christopher Saint, Judy Saint.pdf 39.5 MB
  • Introduction to CMOS OP-AMPS and Comparators.Roubik Gregorian.pdf 187.6 MB
  • The ART of Analog Layout.Alan Hastings/appa.pdf 45.7 kB
  • The ART of Analog Layout.Alan Hastings/appb.pdf 153.4 kB
  • The ART of Analog Layout.Alan Hastings/appc.pdf 216.0 kB
  • The ART of Analog Layout.Alan Hastings/appd.pdf 114.9 kB
  • The ART of Analog Layout.Alan Hastings/appe.pdf 21.0 kB
  • The ART of Analog Layout.Alan Hastings/ch01.pdf 1.8 MB
  • The ART of Analog Layout.Alan Hastings/ch02.pdf 1.7 MB
  • The ART of Analog Layout.Alan Hastings/ch03.pdf 2.2 MB
  • The ART of Analog Layout.Alan Hastings/ch04.pdf 1.9 MB
  • The ART of Analog Layout.Alan Hastings/ch05.pdf 1.8 MB
  • The ART of Analog Layout.Alan Hastings/ch06.pdf 1.1 MB
  • The ART of Analog Layout.Alan Hastings/ch07.pdf 3.2 MB
  • The ART of Analog Layout.Alan Hastings/ch08.pdf 2.5 MB
  • The ART of Analog Layout.Alan Hastings/ch09.pdf 2.8 MB
  • The ART of Analog Layout.Alan Hastings/ch10.pdf 940.9 kB
  • The ART of Analog Layout.Alan Hastings/ch11.pdf 2.1 MB
  • The ART of Analog Layout.Alan Hastings/ch12.pdf 2.5 MB
  • The ART of Analog Layout.Alan Hastings/ch13.pdf 2.5 MB
  • The ART of Analog Layout.Alan Hastings/ch14.pdf 1.5 MB
  • The ART of Analog Layout.Alan Hastings/contents.pdf 624.9 kB
  • The ART of Analog Layout.Alan Hastings/index.pdf 414.9 kB
  • The ART of Analog Layout.Alan Hastings/preface.pdf 60.5 kB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter00.pdf 601.8 kB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter01.pdf 5.1 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter02.pdf 3.9 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter03.pdf 3.2 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter04.pdf 3.6 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter05.pdf 4.6 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter06.pdf 2.6 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter07.pdf 10.7 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter08.pdf 14.6 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter09.pdf 3.0 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter10.pdf 4.0 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter11.pdf 9.1 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter12.pdf 4.0 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter13.pdf 8.5 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter14.pdf 11.7 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter15.pdf 11.8 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter16.pdf 10.0 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter17.pdf 2.5 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter18.pdf 3.0 MB
  • The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter19.pdf 1.9 MB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch1.pdf 235.7 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch2.pdf 223.5 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch3.pdf 219.8 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch4.pdf 222.0 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch5.pdf 234.3 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/chA.pdf 223.7 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/contents.pdf 209.9 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/dg-vams1-errata.pdf 71.1 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/index.pdf 225.5 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/preface.pdf 208.4 kB
  • The Designer's Guide to Verilog-AMS.Kundert, Zinke/references.pdf 204.8 kB
  • Текстовый документ.txt 1.4 kB

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