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[ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification
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[ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification
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文件列表
~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.mp4
118.4 MB
~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.mp4
114.0 MB
~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).mp4
108.0 MB
~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.mp4
81.8 MB
~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).mp4
73.4 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.mp4
62.3 MB
~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.mp4
53.5 MB
~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).mp4
53.3 MB
~Get Your Files Here !/1. Introduction/2. Course overview.mp4
52.9 MB
~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.mp4
52.3 MB
~Get Your Files Here !/1. Introduction/1. Welcome!.mp4
45.8 MB
~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.mp4
44.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.mp4
41.9 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.mp4
41.7 MB
~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.mp4
40.9 MB
~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.mp4
40.5 MB
~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.mp4
39.5 MB
~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.mp4
39.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.mp4
38.5 MB
~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.mp4
38.0 MB
~Get Your Files Here !/4. Verilog Module/1. Verilog Module - the basics.mp4
36.6 MB
~Get Your Files Here !/5. Verilog Design Styles/15. Action Time - 4bit_full_adder structural.mp4
35.7 MB
~Get Your Files Here !/11. Verilog State Machines/1. Discover Finite State Machines.mp4
35.6 MB
~Get Your Files Here !/8. Verilog Sequential Design/12. Action Time - Shift_Reg_SIPO.mp4
35.2 MB
~Get Your Files Here !/7. Verilog Combinational Design/23. Action Time - HEX 7segment decoder.mp4
33.8 MB
~Get Your Files Here !/8. Verilog Sequential Design/21. Action Time - Modulo_N Counter.mp4
33.7 MB
~Get Your Files Here !/11. Verilog State Machines/5. Action Time - Sequence Detector NON Overlaping.mp4
32.4 MB
~Get Your Files Here !/1. Introduction/4. Understand Abstraction Levels.mp4
32.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/2. Action Time - Clocks Generator.mp4
30.6 MB
~Get Your Files Here !/4. Verilog Module/2. Action time - Do your first testbench.mp4
30.6 MB
~Get Your Files Here !/7. Verilog Combinational Design/21. Action Time - demux_4x_nbit.mp4
30.5 MB
~Get Your Files Here !/7. Verilog Combinational Design/13. Action Time - 4to16 binary Decoder.mp4
30.1 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/7. Action Time - Nbit Comparator Function.mp4
29.6 MB
~Get Your Files Here !/11. Verilog State Machines/7. Verilog Mealy FSM Template.mp4
29.5 MB
~Get Your Files Here !/8. Verilog Sequential Design/6. Basics of edge-triggered logic.mp4
29.3 MB
~Get Your Files Here !/10. Verilog Memory Design/1. Basics of Semiconductor Memory.mp4
28.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/11. Action Time - Shift_Reg_PIPO.mp4
27.1 MB
~Get Your Files Here !/12. Verilog Design Examples/4. Basics of Data Ecryption.mp4
26.9 MB
~Get Your Files Here !/8. Verilog Sequential Design/1. Sequential Logic Basics.mp4
26.7 MB
~Get Your Files Here !/7. Verilog Combinational Design/22. Master the Seven Segment Display Decoder.mp4
26.6 MB
~Get Your Files Here !/10. Verilog Memory Design/3. Action Time - Single Port Sync Read SRAM.mp4
26.0 MB
~Get Your Files Here !/8. Verilog Sequential Design/19. Action Time - Nbit Counter.mp4
24.6 MB
~Get Your Files Here !/7. Verilog Combinational Design/14. Action Time - 8to3 Encoder.mp4
24.5 MB
~Get Your Files Here !/12. Verilog Design Examples/1. Discover the First In First Out (FIFO) circuit.mp4
23.9 MB
~Get Your Files Here !/8. Verilog Sequential Design/23. Action Time - Clock Divider Nbit.mp4
23.8 MB
~Get Your Files Here !/7. Verilog Combinational Design/19. Action Time - mux_4x_nbit.mp4
23.8 MB
~Get Your Files Here !/7. Verilog Combinational Design/9. Action Time - Nbit Comparator.mp4
23.7 MB
~Get Your Files Here !/7. Verilog Combinational Design/11. Action Time - Nbit Decoder.mp4
23.6 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/8. Action time - Vectors.mp4
23.6 MB
~Get Your Files Here !/5. Verilog Design Styles/3. Action Time - half adder structural.mp4
23.6 MB
~Get Your Files Here !/6. Verilog Structural Design/4. Discover the Multiplexer.mp4
23.5 MB
~Get Your Files Here !/8. Verilog Sequential Design/10. Discover the Shift Register.mp4
23.5 MB
~Get Your Files Here !/7. Verilog Combinational Design/8. Action Time - Nbit Adder.mp4
23.3 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/1. Verilog Functions Basics.mp4
22.5 MB
~Get Your Files Here !/1. Introduction/5. Discover the Modern Digital Design Flow.mp4
22.2 MB
~Get Your Files Here !/6. Verilog Structural Design/13. Action Time - 1bit_comparator.mp4
21.7 MB
~Get Your Files Here !/8. Verilog Sequential Design/13. Action Time - Shift_Reg_SISO.mp4
21.3 MB
~Get Your Files Here !/7. Verilog Combinational Design/24. How to use digital logic for arithmetic operations.mp4
21.2 MB
~Get Your Files Here !/8. Verilog Sequential Design/18. Discover Synchronous Counters.mp4
20.9 MB
~Get Your Files Here !/2. Install the Simulator/2. Install Intel Quartus Prime Lite and Modelsim.mp4
20.9 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/13. Discover Automated Verification.mp4
20.8 MB
~Get Your Files Here !/7. Verilog Combinational Design/4. Action Time - Adder Tree.mp4
20.7 MB
~Get Your Files Here !/8. Verilog Sequential Design/22. Discover Digital Frequency Dividers.mp4
20.4 MB
~Get Your Files Here !/7. Verilog Combinational Design/1. What is Combinational logic.mp4
20.4 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/6. Action time - Literal values.mp4
20.3 MB
~Get Your Files Here !/7. Verilog Combinational Design/5. Discover Procedural Assignments.mp4
20.1 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/10. Action Time - Verilog Tasks Control Shift Reg.mp4
20.0 MB
~Get Your Files Here !/8. Verilog Sequential Design/3. Types of Sequential Digital Logic.mp4
20.0 MB
~Get Your Files Here !/6. Verilog Structural Design/7. Action Time -1bit_demux.mp4
19.9 MB
~Get Your Files Here !/6. Verilog Structural Design/2. Verilog Built-in_Primitives.mp4
19.9 MB
~Get Your Files Here !/5. Verilog Design Styles/13. Action Time - full_adder behavioral.mp4
19.6 MB
~Get Your Files Here !/2. Install the Simulator/3. Action Time - Hello World using Verilog.mp4
19.4 MB
~Get Your Files Here !/5. Verilog Design Styles/5. Action Time - half_adder dataflow.mp4
19.2 MB
~Get Your Files Here !/7. Verilog Combinational Design/17. Action Time - Priority Encoder2 4to2.mp4
18.8 MB
~Get Your Files Here !/5. Verilog Design Styles/11. Action Time - full_adder structural.mp4
18.8 MB
~Get Your Files Here !/7. Verilog Combinational Design/16. Action Time - Priority Encoder1 4to2.mp4
18.8 MB
~Get Your Files Here !/2. Install the Simulator/1. Discover the Verilog Simulation.mp4
18.4 MB
~Get Your Files Here !/8. Verilog Sequential Design/4. Action Time - The D_Latch.mp4
18.3 MB
~Get Your Files Here !/5. Verilog Design Styles/16. Action Time - 4bit_full_adder dataflow.mp4
18.1 MB
~Get Your Files Here !/1. Introduction/3. What is Verilog HDL.mp4
18.1 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/4. Action time - Multiple procedures.mp4
18.0 MB
~Get Your Files Here !/7. Verilog Combinational Design/15. What is a Priority Encoder.mp4
17.5 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/29. Action Time - Replication Operator.mp4
17.5 MB
~Get Your Files Here !/6. Verilog Structural Design/5. Action Time - 1bit_mux.mp4
17.4 MB
~Get Your Files Here !/8. Verilog Sequential Design/5. Action Time - D_Latch_reset_n.mp4
17.3 MB
~Get Your Files Here !/12. Verilog Design Examples/6. Congratulations!.mp4
17.3 MB
~Get Your Files Here !/7. Verilog Combinational Design/6. Action Time - Tree Adder Procedural.mp4
17.1 MB
~Get Your Files Here !/4. Verilog Module/6. Action Time - Generate Waveforms.mp4
16.9 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/5. Action Time - Verilog Functions Factorial.mp4
16.5 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/3. Hardware Description Language data types.mp4
16.5 MB
~Get Your Files Here !/8. Verilog Sequential Design/8. Action Time - D_Flip_Flop_async_rstn.mp4
16.3 MB
~Get Your Files Here !/8. Verilog Sequential Design/16. Discover the Linear Feedback Shift Register.mp4
16.2 MB
~Get Your Files Here !/6. Verilog Structural Design/6. Discover the Demultiplexer.mp4
16.2 MB
~Get Your Files Here !/7. Verilog Combinational Design/10. Differentiate between binary encoders and decoders.mp4
16.2 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/1. Verilog Data types overview.mp4
16.1 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/4. Discover Verilog Recursive Functions.mp4
16.0 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/15. Action Time - Logical Operators usage.mp4
15.8 MB
~Get Your Files Here !/6. Verilog Structural Design/11. Action Time - mux_tri-state.mp4
15.8 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/2. Action time - sum and product.mp4
15.7 MB
~Get Your Files Here !/5. Verilog Design Styles/10. Design a 1bit full_adder.mp4
15.3 MB
~Get Your Files Here !/5. Verilog Design Styles/8. Action Time - Initial Procedures.mp4
15.1 MB
~Get Your Files Here !/7. Verilog Combinational Design/3. Action Time - Continuous assignments.mp4
15.1 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/11. Why our code looks like software.mp4
15.0 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/12. Action Time - Reduction operators.mp4
14.8 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/27. Action Time - Concatenation Operator.mp4
14.5 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/10. Action Time - Bit-wise operators.mp4
14.3 MB
~Get Your Files Here !/5. Verilog Design Styles/1. What are HDL Design Styles.mp4
14.2 MB
~Get Your Files Here !/5. Verilog Design Styles/9. Action Time - half_adder behavioral.mp4
13.8 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/31. Action Time - Operators Precedence.mp4
13.2 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/2. Action Time - Verilog Functions1.mp4
13.2 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/5. What are Literal Values.mp4
12.9 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/25. Action Time - Conditional Operator.mp4
12.9 MB
~Get Your Files Here !/7. Verilog Combinational Design/18. Discover bus Multiplexers.mp4
12.6 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/9. Verilog Operators - Bit-wise.mp4
12.6 MB
~Get Your Files Here !/11. Verilog State Machines/6. Action Time - Sequence Detector Overlaping.mp4
12.5 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/18. Verilog Operators - Shift.mp4
12.2 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/19. Action Time - Shift Operators.mp4
12.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/9. Remember!.mp4
12.0 MB
~Get Your Files Here !/5. Verilog Design Styles/17. Action Time - 4bit_full_adder behavioral.mp4
12.0 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/6. Action Time - Verilog Functions Fibonacci.mp4
12.0 MB
~Get Your Files Here !/5. Verilog Design Styles/12. Action Time - full_adder dataflow.mp4
11.7 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/9. Action Time - Verilog Tasks Distance Conversion.mp4
11.5 MB
~Get Your Files Here !/2. Install the Simulator/4. Congratulations!.mp4
11.4 MB
~Get Your Files Here !/7. Verilog Combinational Design/2. Discover Continuous assignments.mp4
11.2 MB
~Get Your Files Here !/11. Verilog State Machines/4. Basics of Sequence Detectors.mp4
11.0 MB
~Get Your Files Here !/6. Verilog Structural Design/9. Action Time - tri-state_buffer.mp4
11.0 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/21. Action Time - Relational Operators.mp4
11.0 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/7. Vectors in Verilog.mp4
11.0 MB
~Get Your Files Here !/4. Verilog Module/5. Discover Time and Waveforms.mp4
10.7 MB
~Get Your Files Here !/5. Verilog Design Styles/2. Verilog Structural Design.mp4
10.7 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/3. Action Time - Verilog Functions2.mp4
10.7 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/14. Action Time - Logical Operators.mp4
10.6 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/22. Verilog Operators - Equality.mp4
10.5 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/8. Verilog Tasks Basics.mp4
10.4 MB
~Get Your Files Here !/6. Verilog Structural Design/3. Action Time - Built-in_gates.mp4
10.2 MB
~Get Your Files Here !/5. Verilog Design Styles/14. Design a 4bit full_adder.mp4
10.0 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/28. Verilog Operators - Replication.mp4
9.9 MB
~Get Your Files Here !/6. Verilog Structural Design/10. How to implement a multiplexer using tri-state buffers.mp4
9.9 MB
~Get Your Files Here !/7. Verilog Combinational Design/12. How to use multiple binary decoders.mp4
9.7 MB
~Get Your Files Here !/6. Verilog Structural Design/1. What is Structural Design.mp4
9.7 MB
~Get Your Files Here !/4. Verilog Module/4. What is a Testbench Architecture.mp4
9.7 MB
~Get Your Files Here !/7. Verilog Combinational Design/20. Discover bus Demultiplexers.mp4
9.1 MB
~Get Your Files Here !/5. Verilog Design Styles/18. Congratulations!.mp4
9.0 MB
~Get Your Files Here !/6. Verilog Structural Design/8. The Tri-state buffer.mp4
8.8 MB
~Get Your Files Here !/6. Verilog Structural Design/14. Remember!.mp4
8.5 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/13. Verilog Operators - Logical.mp4
8.2 MB
~Get Your Files Here !/4. Verilog Module/3. Remember!.mp4
8.0 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/17. Action Time - Arithmetic Operators.mp4
7.9 MB
~Get Your Files Here !/7. Verilog Combinational Design/7. Discover the Nbit Adder.mp4
7.6 MB
~Get Your Files Here !/5. Verilog Design Styles/4. Verilog Dataflow style.mp4
7.6 MB
~Get Your Files Here !/7. Verilog Combinational Design/26. Remember!.mp4
7.6 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/23. Action Time - Equality Operators.mp4
7.3 MB
~Get Your Files Here !/5. Verilog Design Styles/7. Remember!.mp4
7.2 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/24. Verilog Operators - Conditional.mp4
7.0 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/32. Congratulations!.mp4
6.7 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/26. Verilog Operators - Concatenation.mp4
6.7 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/20. Verilog Operators - Relational.mp4
6.6 MB
~Get Your Files Here !/6. Verilog Structural Design/12. Discover the 1bit Comparator.mp4
6.3 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/30. Verilog Operators - Precedence.mp4
5.1 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/11. Verilog Operators - Reduction.mp4
4.6 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/16. Verilog Operators - Arithmetic.mp4
3.8 MB
~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.srt
14.9 kB
~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.srt
14.4 kB
~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).srt
14.0 kB
~Get Your Files Here !/7. Verilog Combinational Design/14.1 encoder_8to3.v
11.7 kB
~Get Your Files Here !/8. Verilog Sequential Design/11.1 shift_reg_pipo.v
11.5 kB
~Get Your Files Here !/7. Verilog Combinational Design/17.1 prio_enc2_4to2.v
11.3 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/4.1 easy_verilog_example.v
11.1 kB
~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.srt
10.7 kB
~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).srt
10.2 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/14.1 ALU.v
7.2 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.srt
6.9 kB
~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).srt
6.8 kB
~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.srt
6.7 kB
~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.srt
6.6 kB
~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.srt
6.0 kB
~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.srt
5.9 kB
~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.srt
5.3 kB
~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.srt
5.3 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.srt
5.2 kB
~Get Your Files Here !/1. Introduction/2. Course overview.srt
5.0 kB
~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.srt
4.9 kB
~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.srt
4.9 kB
~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.srt
4.8 kB
~Get Your Files Here !/10. Verilog Memory Design/4.1 ram_dp_async_read.v
4.5 kB
~Get Your Files Here !/1. Introduction/1. Welcome!.srt
4.5 kB
~Get Your Files Here !/12. Verilog Design Examples/5.3 tb_encrypt.v
4.4 kB
~Get Your Files Here !/11. Verilog State Machines/1. Discover Finite State Machines.srt
4.3 kB
~Get Your Files Here !/4. Verilog Module/2. Action time - Do your first testbench.srt
4.3 kB
~Get Your Files Here !/8. Verilog Sequential Design/12. Action Time - Shift_Reg_SIPO.srt
4.3 kB
~Get Your Files Here !/8. Verilog Sequential Design/21. Action Time - Modulo_N Counter.srt
4.2 kB
~Get Your Files Here !/4. Verilog Module/1. Verilog Module - the basics.srt
4.1 kB
~Get Your Files Here !/7. Verilog Combinational Design/13. Action Time - 4to16 binary Decoder.srt
4.1 kB
~Get Your Files Here !/11. Verilog State Machines/5. Action Time - Sequence Detector NON Overlaping.srt
4.1 kB
~Get Your Files Here !/8. Verilog Sequential Design/2. Action Time - Clocks Generator.srt
4.0 kB
~Get Your Files Here !/5. Verilog Design Styles/15. Action Time - 4bit_full_adder structural.srt
3.9 kB
~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.srt
3.9 kB
~Get Your Files Here !/5. Verilog Design Styles/3. Action Time - half adder structural.srt
3.8 kB
~Get Your Files Here !/11. Verilog State Machines/3.1 semaphore_fsm.v
3.8 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/7. Action Time - Nbit Comparator Function.srt
3.8 kB
~Get Your Files Here !/2. Install the Simulator/3. Action Time - Hello World using Verilog.srt
3.7 kB
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3.7 kB
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3.6 kB
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3.6 kB
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3.5 kB
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3.5 kB
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3.5 kB
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3.5 kB
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3.4 kB
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3.4 kB
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3.4 kB
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3.3 kB
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3.3 kB
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3.3 kB
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3.3 kB
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3.3 kB
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3.2 kB
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3.2 kB
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3.2 kB
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3.1 kB
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3.1 kB
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3.1 kB
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3.1 kB
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3.0 kB
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3.0 kB
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2.9 kB
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2.8 kB
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2.8 kB
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2.7 kB
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2.7 kB
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2.7 kB
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2.6 kB
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2.6 kB
~Get Your Files Here !/5. Verilog Design Styles/16.1 ripple_adder_4bit_dataflow.v
2.6 kB
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2.6 kB
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2.6 kB
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2.5 kB
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2.5 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/12.1 shift_reg_pipo_buggy.v
2.5 kB
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2.5 kB
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2.5 kB
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2.5 kB
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2.5 kB
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2.5 kB
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2.4 kB
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2.4 kB
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2.4 kB
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2.4 kB
~Get Your Files Here !/12. Verilog Design Examples/1. Discover the First In First Out (FIFO) circuit.srt
2.4 kB
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2.4 kB
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2.4 kB
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2.4 kB
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2.3 kB
~Get Your Files Here !/5. Verilog Design Styles/16. Action Time - 4bit_full_adder dataflow.srt
2.3 kB
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2.3 kB
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2.2 kB
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2.2 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/5. Action Time - Verilog Functions Factorial.srt
2.2 kB
~Get Your Files Here !/7. Verilog Combinational Design/17. Action Time - Priority Encoder2 4to2.srt
2.2 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/1. Verilog Functions Basics.srt
2.2 kB
~Get Your Files Here !/8. Verilog Sequential Design/3. Types of Sequential Digital Logic.srt
2.2 kB
~Get Your Files Here !/8. Verilog Sequential Design/15.1 shift_left_right_load_reg.v
2.1 kB
~Get Your Files Here !/8. Verilog Sequential Design/20.1 counter_up_down_load_nbit.v
2.1 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/6. Action time - Literal values.srt
2.1 kB
~Get Your Files Here !/6. Verilog Structural Design/2. Verilog Built-in_Primitives.srt
2.1 kB
~Get Your Files Here !/8. Verilog Sequential Design/22. Discover Digital Frequency Dividers.srt
2.1 kB
~Get Your Files Here !/7. Verilog Combinational Design/1. What is Combinational logic.srt
2.0 kB
~Get Your Files Here !/8. Verilog Sequential Design/24.1 clock_div_3.v
2.0 kB
~Get Your Files Here !/6. Verilog Structural Design/6. Discover the Demultiplexer.srt
2.0 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/10. Action Time - Bit-wise operators.srt
2.0 kB
~Get Your Files Here !/7. Verilog Combinational Design/15. What is a Priority Encoder.srt
1.9 kB
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1.9 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/10.1 task_control_shift_reg.v
1.9 kB
~Get Your Files Here !/2. Install the Simulator/2. Install Intel Quartus Prime Lite and Modelsim.srt
1.9 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/2. Action Time - Verilog Functions1.srt
1.8 kB
~Get Your Files Here !/7. Verilog Combinational Design/5. Discover Procedural Assignments.srt
1.8 kB
~Get Your Files Here !/4. Verilog Module/6. Action Time - Generate Waveforms.srt
1.8 kB
~Get Your Files Here !/8. Verilog Sequential Design/23.1 clock_div_nbit.v
1.8 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/29. Action Time - Replication Operator.srt
1.8 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/15. Action Time - Logical Operators usage.srt
1.8 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/15.1 logical_operators_usage.v
1.8 kB
~Get Your Files Here !/8. Verilog Sequential Design/16. Discover the Linear Feedback Shift Register.srt
1.8 kB
~Get Your Files Here !/5. Verilog Design Styles/11.1 full_adder_structural.v
1.8 kB
~Get Your Files Here !/7. Verilog Combinational Design/13.1 decoder_4to16.v
1.8 kB
~Get Your Files Here !/7. Verilog Combinational Design/10. Differentiate between binary encoders and decoders.srt
1.7 kB
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1.7 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/27. Action Time - Concatenation Operator.srt
1.7 kB
~Get Your Files Here !/7. Verilog Combinational Design/23.1 hex_7seg_decoder.v
1.7 kB
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1.7 kB
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1.7 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/4. Discover Verilog Recursive Functions.srt
1.6 kB
~Get Your Files Here !/5. Verilog Design Styles/10. Design a 1bit full_adder.srt
1.6 kB
~Get Your Files Here !/1. Introduction/3. What is Verilog HDL.srt
1.6 kB
~Get Your Files Here !/10. Verilog Memory Design/5.2 rom.v
1.6 kB
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1.6 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/9. Verilog Operators - Bit-wise.srt
1.6 kB
~Get Your Files Here !/5. Verilog Design Styles/9. Action Time - half_adder behavioral.srt
1.6 kB
~Get Your Files Here !/8. Verilog Sequential Design/14.1 shift_reg_piso.v
1.6 kB
~Get Your Files Here !/11. Verilog State Machines/6. Action Time - Sequence Detector Overlaping.srt
1.6 kB
~Get Your Files Here !/5. Verilog Design Styles/12. Action Time - full_adder dataflow.srt
1.6 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/7.1 compare_nbit_func.v
1.6 kB
~Get Your Files Here !/7. Verilog Combinational Design/18. Discover bus Multiplexers.srt
1.5 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/1. Verilog Data types overview.srt
1.5 kB
~Get Your Files Here !/8. Verilog Sequential Design/21.1 counter_modulo_n.v
1.5 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/19. Action Time - Shift Operators.srt
1.5 kB
~Get Your Files Here !/8. Verilog Sequential Design/12.1 shift_reg_sipo.v
1.5 kB
~Get Your Files Here !/2. Install the Simulator/1. Discover the Verilog Simulation.srt
1.5 kB
~Get Your Files Here !/5. Verilog Design Styles/17. Action Time - 4bit_full_adder behavioral.srt
1.5 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/31. Action Time - Operators Precedence.srt
1.5 kB
~Get Your Files Here !/7. Verilog Combinational Design/6.1 adders3_procedural.v
1.5 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/11. Why our code looks like software.srt
1.4 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/9. Action Time - Verilog Tasks Distance Conversion.srt
1.4 kB
~Get Your Files Here !/8. Verilog Sequential Design/13.1 shift_reg_siso.v
1.4 kB
~Get Your Files Here !/7. Verilog Combinational Design/19.1 mux_4x_nbit.v
1.4 kB
~Get Your Files Here !/7. Verilog Combinational Design/21.1 demux_nbit_x4.v
1.4 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/6. Action Time - Verilog Functions Fibonacci.srt
1.4 kB
~Get Your Files Here !/5. Verilog Design Styles/12.1 full_adder_dataflow.v
1.4 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/21. Action Time - Relational Operators.srt
1.4 kB
~Get Your Files Here !/8. Verilog Sequential Design/8.1 d_ff_async_rstn.v
1.4 kB
~Get Your Files Here !/8. Verilog Sequential Design/7.1 d_ff_sync_rstn.v
1.3 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/25. Action Time - Conditional Operator.srt
1.3 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/3. Action Time - Verilog Functions2.srt
1.3 kB
~Get Your Files Here !/7. Verilog Combinational Design/20. Discover bus Demultiplexers.srt
1.3 kB
~Get Your Files Here !/5. Verilog Design Styles/2. Verilog Structural Design.srt
1.3 kB
~Get Your Files Here !/8. Verilog Sequential Design/17.1 lfsr_16.v
1.3 kB
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1.3 kB
~Get Your Files Here !/4. Verilog Module/4. What is a Testbench Architecture.srt
1.3 kB
~Get Your Files Here !/7. Verilog Combinational Design/9.1 comparator_nbit.v
1.3 kB
~Get Your Files Here !/4. Verilog Module/5. Discover Time and Waveforms.srt
1.3 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/14. Action Time - Logical Operators.srt
1.3 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/31.1 operators_precedence.v
1.3 kB
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1.3 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/14.1 logical_operators.v
1.2 kB
~Get Your Files Here !/8. Verilog Sequential Design/5.1 d_latch_rstn.v
1.2 kB
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1.2 kB
~Get Your Files Here !/8. Verilog Sequential Design/19.1 counter_nbit.v
1.2 kB
~Get Your Files Here !/5. Verilog Design Styles/17.1 adder_4bit_behavioral.v
1.2 kB
~Get Your Files Here !/2. Install the Simulator/4. Congratulations!.srt
1.2 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/10.1 bitwise_operators.v
1.2 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/5. What are Literal Values.srt
1.2 kB
~Get Your Files Here !/5. Verilog Design Styles/1. What are HDL Design Styles.srt
1.2 kB
~Get Your Files Here !/12. Verilog Design Examples/5.4 top_encrypt_golden.v
1.2 kB
~Get Your Files Here !/6. Verilog Structural Design/10. How to implement a multiplexer using tri-state buffers.srt
1.2 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/23.1 equality_operators.v
1.2 kB
~Get Your Files Here !/7. Verilog Combinational Design/16.1 prio_enc1_4to2.v
1.2 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/22. Verilog Operators - Equality.srt
1.1 kB
~Get Your Files Here !/9. Verilog Functions and Tasks/8. Verilog Tasks Basics.srt
1.1 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/18. Verilog Operators - Shift.srt
1.1 kB
~Get Your Files Here !/7. Verilog Combinational Design/2. Discover Continuous assignments.srt
1.1 kB
~Get Your Files Here !/12. Verilog Design Examples/6. Congratulations!.srt
1.1 kB
~Get Your Files Here !/11. Verilog State Machines/4. Basics of Sequence Detectors.srt
1.1 kB
~Get Your Files Here !/5. Verilog Design Styles/8.1 procedures.v
1.1 kB
~Get Your Files Here !/7. Verilog Combinational Design/4.1 adders3.v
1.1 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/12.1 reduction_operators.v
1.1 kB
~Get Your Files Here !/7. Verilog Combinational Design/12. How to use multiple binary decoders.srt
1.1 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/8.1 easy_vectors_example.v
1.1 kB
~Get Your Files Here !/6. Verilog Structural Design/8. The Tri-state buffer.srt
1.1 kB
~Get Your Files Here !/8. Verilog Sequential Design/9. Remember!.srt
1.1 kB
~Get Your Files Here !/8. Verilog Sequential Design/4.1 d_latch.v
1.1 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/7. Vectors in Verilog.srt
1.0 kB
~Get Your Files Here !/3. Verilog Data Types and Operators/28. Verilog Operators - Replication.srt
1.0 kB
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1.0 kB
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1.0 kB
~Get Your Files Here !/7. Verilog Combinational Design/8.1 adder_nbit.v
1.0 kB
~Get Your Files Here !/12. Verilog Design Examples/5.5 top_encrypt.v
990 Bytes
~Get Your Files Here !/7. Verilog Combinational Design/11.1 decoder_nbit.v
968 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/17. Action Time - Arithmetic Operators.srt
948 Bytes
~Get Your Files Here !/5. Verilog Design Styles/3.1 half_adder_structural.v
946 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/6.1 literal_values.v
940 Bytes
~Get Your Files Here !/6. Verilog Structural Design/13.1 comparator_1bit.v
936 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/13. Verilog Operators - Logical.srt
933 Bytes
~Get Your Files Here !/5. Verilog Design Styles/9.1 half_adder_behavioral.v
928 Bytes
~Get Your Files Here !/11. Verilog State Machines/7.1 fsm_template.v
911 Bytes
~Get Your Files Here !/5. Verilog Design Styles/5.1 half_adder_dataflow.v
906 Bytes
~Get Your Files Here !/5. Verilog Design Styles/18. Congratulations!.srt
866 Bytes
~Get Your Files Here !/8. Verilog Sequential Design/2.1 clkgen.v
857 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/19.1 shift_operators.v
829 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/29.1 replication_operator.v
828 Bytes
~Get Your Files Here !/9. Verilog Functions and Tasks/9.1 task_meters_to_feet.v
806 Bytes
~Get Your Files Here !/5. Verilog Design Styles/4. Verilog Dataflow style.srt
799 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/11. Verilog Operators - Reduction.srt
784 Bytes
~Get Your Files Here !/6. Verilog Structural Design/11.1 mux_tristate.v
784 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/23. Action Time - Equality Operators.srt
768 Bytes
~Get Your Files Here !/7. Verilog Combinational Design/7. Discover the Nbit Adder.srt
767 Bytes
~Get Your Files Here !/6. Verilog Structural Design/12. Discover the 1bit Comparator.srt
766 Bytes
~Get Your Files Here !/7. Verilog Combinational Design/3.1 some_logic.v
762 Bytes
~Get Your Files Here !/4. Verilog Module/2.2 my_first_testbench.v
758 Bytes
~Get Your Files Here !/6. Verilog Structural Design/14. Remember!.srt
728 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/32. Congratulations!.srt
714 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/30. Verilog Operators - Precedence.srt
709 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/26. Verilog Operators - Concatenation.srt
704 Bytes
~Get Your Files Here !/9. Verilog Functions and Tasks/6.1 function_ex4.v
688 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/24. Verilog Operators - Conditional.srt
671 Bytes
~Get Your Files Here !/4. Verilog Module/3. Remember!.srt
667 Bytes
~Get Your Files Here !/6. Verilog Structural Design/3.1 built_in_gates.v
667 Bytes
~Get Your Files Here !/6. Verilog Structural Design/3.2 tb_gates.v
661 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/25.1 conditional_operators.v
648 Bytes
~Get Your Files Here !/9. Verilog Functions and Tasks/5.1 function_ex3.v
633 Bytes
~Get Your Files Here !/7. Verilog Combinational Design/26. Remember!.srt
628 Bytes
~Get Your Files Here !/5. Verilog Design Styles/7. Remember!.srt
626 Bytes
~Get Your Files Here !/6. Verilog Structural Design/7.2 tb_demux.v
623 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/20. Verilog Operators - Relational.srt
618 Bytes
~Get Your Files Here !/12. Verilog Design Examples/3.1 ram_dp_async_read.v
609 Bytes
~Get Your Files Here !/9. Verilog Functions and Tasks/2.1 function_ex1.v
588 Bytes
~Get Your Files Here !/12. Verilog Design Examples/5.1 prng.v
570 Bytes
~Get Your Files Here !/9. Verilog Functions and Tasks/3.1 function_ex2.v
557 Bytes
~Get Your Files Here !/6. Verilog Structural Design/9.1 tb_tristate.v
539 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/21.1 relational_operators.v
507 Bytes
~Get Your Files Here !/6. Verilog Structural Design/5.2 tb_mux.v
506 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/2.1 sum_product.v
433 Bytes
~Get Your Files Here !/4. Verilog Module/6.1 waveforms.v
425 Bytes
~Get Your Files Here !/3. Verilog Data Types and Operators/16. Verilog Operators - Arithmetic.srt
413 Bytes
~Get Your Files Here !/Bonus Resources.txt
357 Bytes
~Get Your Files Here !/6. Verilog Structural Design/5.1 mux_1bit.v
271 Bytes
~Get Your Files Here !/6. Verilog Structural Design/7.1 demux_1bit.v
224 Bytes
~Get Your Files Here !/2. Install the Simulator/3.1 hello_world.v
208 Bytes
Get Bonus Downloads Here.url
180 Bytes
~Get Your Files Here !/6. Verilog Structural Design/9.2 tristate_buffer_1bit.v
137 Bytes
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133 Bytes
~Get Your Files Here !/12. Verilog Design Examples/5.2 secret_message.txt
110 Bytes
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66 Bytes
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