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- [ DevCourseWeb.com ] Udemy - Verilog on Intel (Altera) FPGA.zip 3.1 GB
- Beginners Course to FPGA Development in VHDL.tgz 447.2 MB
- Torrent downloaded from demonoid.pw.txt 46 Bytes
- Torrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
- ~Get Your Files Here !/6 - Pointers/35 - MultiAccess Pointers on the Interface.mp4 260.9 MB
- ~Get Your Files Here !/9 - HLS Stream Library/55 - Stream on the Interface.mp4 194.9 MB
- ~Get Your Files Here !/9 - HLS Stream Library/56 - BlockingNonBlocking.mp4 185.4 MB
- ~Get Your Files Here !/2 - LAB Setup/5 - Linux Installation.mp4 180.1 MB
- ~Get Your Files Here !/7 - AXI in HLS/44 - The maxi interface.mp4 161.8 MB
- ~Get Your Files Here !/3 - MultiCycle Design/14 - BlockLevel Handshake.mp4 154.1 MB
- ~Get Your Files Here !/6 - Pointers/34 - Pointer Arithmetic.mp4 132.5 MB
- ~Get Your Files Here !/6 - Pointers/31 - Definition.mp4 128.2 MB
- ~Get Your Files Here !/7 - AXI in HLS/40 - Memory Mapped Output 01.mp4 127.5 MB
- ~Get Your Files Here !/3 - MultiCycle Design/9 - Example.mp4 125.2 MB
- ~Get Your Files Here !/3 - MultiCycle Design/12 - Example with ack.mp4 125.0 MB
- ~Get Your Files Here !/4 - Streaming/21 - Streaming Example Vivado.mp4 121.5 MB
- ~Get Your Files Here !/7 - AXI in HLS/43 - Memory Mapped IO.mp4 116.3 MB
- ~Get Your Files Here !/3 - MultiCycle Design/11 - Example with vld.mp4 112.4 MB
- ~Get Your Files Here !/6 - Pointers/33 - Pointers on the Interface.mp4 111.2 MB
- ~Get Your Files Here !/8 - Loops In HLS/48 - Loop Unrolling.mp4 110.3 MB
- ~Get Your Files Here !/5 - ArrayInHLS/28 - Array ReadWrite Vivado.mp4 110.0 MB
- ~Get Your Files Here !/7 - AXI in HLS/42 - Memory Mapped Output 02.mp4 100.3 MB
- ~Get Your Files Here !/6 - Pointers/32 - Native Pointer Casting.mp4 95.1 MB
- ~Get Your Files Here !/5 - ArrayInHLS/25 - Array Issues.mp4 92.1 MB
- 7010/ZedBoard/Ubuntu_zz_ftp_ssh_linux.7z 3.4 GB
- 7010/ZedBoard/视频教程发布/51,ZEDBOARD嵌入式LINUX平台搭建.rar 2.4 GB
- 7010/ZedBoard/ov7670采集以及显示系统详解以及实现2016_10_28.rar 1.7 GB
- 7010/EBAZ4205/ebit_linux/TF/pynq_z2_v2.4.zip 1.6 GB
- 7010/ZedBoard/视频教程发布/2，Zedboard上运行桌面LINUX.rar 1.2 GB
- 7010/EBAZ4205/ebit_linux/TF/xillinux-2.0.img.gz 1.2 GB
- FPGA/4205启动xillinux系统/xillinux-2.0.img.gz 1.2 GB
- 7010/4205资料.zip 879.6 MB
- ebaz4205-gathered-by-ustcpetergu.zip 801.8 MB
- 7010/ZedBoard/视频教程发布/22，SPI FLASH里启动LINUX的详细分析和实现.rar 688.1 MB
- 7010/ZedBoard/视频教程发布/8,建立LINUX开发环境并编译LINUX和UBOOT以及生成设备树.rar 646.9 MB
- 7010/ZedBoard/视频教程发布/16，MIO和EMIO下的GPIO分析和实例.rar 641.1 MB
- 7010/ZedBoard/视频教程发布/13，PL和PS协同设计实现对OLED的控制.rar 472.3 MB
- 7010/ZedBoard/视频教程发布/24，VGA接口原理分析以及控制逻辑的实现.rar 458.8 MB
- 7010/ZedBoard/视频教程发布/26，使用VIVADO例化BRAM实现VGA独立缓存驱动.rar 390.5 MB
- 7010/ZedBoard/视频教程发布/17，GPIO中断源的配置以及中断试验.rar 371.9 MB
- 7010/ZedBoard/视频教程发布/18，多路PWM原理分析以及实现试验.rar 346.2 MB
- 7010/ZedBoard/视频教程发布/25，纯PL实现独立显存VGA驱动并显示画面.rar 334.7 MB
- 7010/ZedBoard/视频教程发布/23，QT开发环境的建立以及在ZEDBOARD开发板上运行第一个QT例子.rar 317.1 MB
- 7010/ZedBoard/视频教程发布/12，学习使用VIO以及进行试验.rar 277.0 MB
- [ FreeCourseWeb.com ] Udemy - FPGA Drive 7 Segment Display.zip 1.2 GB
- 8. One Key Module Coding.mp4 190.6 MB
- 2. Make Buzzer Buzzing.mp4 184.6 MB
- 9. One Key Module Simulation.mp4 128.6 MB
- 6. Buzzer Module Simulation.mp4 108.1 MB
- 5. Buzzer Module Coding.mp4 101.6 MB
- 12. Key Module Solution2 Coding.mp4 88.4 MB
- 11. Key Module Solution1 Simultion.mp4 87.2 MB
- 10. Key Module Solution1 Coding.mp4 74.9 MB
- 16. LED Module Simulation.mp4 71.6 MB
- 19. Run on Board.mp4 66.7 MB
- 18. Top Module Simulation.mp4 66.7 MB
- 17. Top Module Coding.mp4 59.1 MB
- 1. System Target.mp4 57.9 MB
- 15. LED Module Coding.mp4 48.3 MB
- 7. Key Module Status Machine.mp4 33.3 MB
- 13. Key Module Solution2 Simulation.mp4 23.1 MB
- 4. Buzzer Module Status Machine.mp4 18.1 MB
- 3. System Analysis.mp4 15.4 MB
- 14. LED Module Status Machine.mp4 10.1 MB
- 8. One Key Module Coding.srt 31.9 kB
- [ DevCourseWeb.com ] Udemy - FPGA Embedded Design, Part 3 - EDA Tools.zip 1.2 GB
- [ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 4 - Microprocessor Design.zip 1.8 GB
- Hardware - Frame/Crab Grab (White case).gnw 3.3 MB
- Hardware - Frame/Crab Grab.gnw 3.3 MB
- Hardware - Frame/Donkey Kong II.gnw 3.3 MB
- Hardware - Frame/Donkey Kong Jr. (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Donkey Kong.gnw 3.3 MB
- Hardware - Frame/Fire Attack (Bandits).gnw 3.3 MB
- Hardware - Frame/Fire Attack.gnw 3.3 MB
- Hardware - Frame/Green House.gnw 3.3 MB
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- Hardware - Frame/Mario Bros..gnw 3.3 MB
- Hardware - Frame/Mario's Cement Factory (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Mickey & Donald.gnw 3.3 MB
- Hardware - Frame/Oil Panic.gnw 3.3 MB
- Hardware - Frame/Rain Shower.gnw 3.3 MB
- Hardware - Frame/Snoopy Tennis.gnw 3.3 MB
- Hardware - Frame/Spitball Sparky (White case).gnw 3.3 MB
- Hardware - Frame/Spitball Sparky.gnw 3.3 MB
- Hardware - Frame/Squish.gnw 3.3 MB
- Hardware - Frame/Tropical Fish.gnw 3.3 MB
- NEOGEO.zip 1.8 GB
- neo-geo-1g1r-darksoft-converted-to-neosd-mister-fpga_meta.sqlite 28.7 kB
- neo-geo-1g1r-darksoft-converted-to-neosd-mister-fpga_meta.xml 3.7 kB
- [ FreeCourseWeb ] Lynda - Learning FPGA Development.rar 177.6 MB
- ~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/1. Section 4 Advance Design with HDL Coder Overview.mp4 162.5 MB
- ~Get Your Files Here !/3. Section_3 Project with System Generator/2. Section 3 Lab 30 Basic Project with System Generator.mp4 122.9 MB
- ~Get Your Files Here !/1. Section_1 Installation of MatlabSimulink and VIVADOISE/1. Installation of MatlabSimulink and VIVADOISE.mp4 74.3 MB
- ~Get Your Files Here !/6. Section_6 Zynq Development with System Generator & VIVADO/1. ZedBoard XADC+ Pmod Interfacing and Implementation on System Generator.mp4 65.7 MB
- ~Get Your Files Here !/3. Section_3 Project with System Generator/1. Section_3 Basic Project with System Generator Overview.mp4 58.3 MB
- ~Get Your Files Here !/2. Section_2 Introduction to HDL Coder and System Generator/1. Introduction to HDL Coder and System Generator Part I.mp4 55.8 MB
- ~Get Your Files Here !/1. Section_1 Installation of MatlabSimulink and VIVADOISE/2. Section 1 Lab 1 Basic Design with Simulink Environment.mp4 51.2 MB
- ~Get Your Files Here !/2. Section_2 Introduction to HDL Coder and System Generator/2. Introduction to HDL Coder and System Generator Part II.mp4 39.1 MB
- ~Get Your Files Here !/5. Section_5 Advanced Design with System Generator/1. Lab 51 FIR Filter Design.mp4 34.3 MB
- ~Get Your Files Here !/3. Section_3 Project with System Generator/3. Lab 31 Basic FFT Design with System Generator.mp4 33.1 MB
- ~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/2. LMS Filter Design_Advance Design with HDL Coder.mp4 29.4 MB
- ~Get Your Files Here !/5. Section_5 Advanced Design with System Generator/2. OFDM Transceiver Design and Simulation Part I Transmitter Section.mp4 19.5 MB
- ~Get Your Files Here !/3. Section_3 Project with System Generator/4. Lab 32 Creating Custom JTAG Configuration.mp4 18.7 MB
- ~Get Your Files Here !/5. Section_5 Advanced Design with System Generator/3. OFDM Transceiver Design and Simulation Part II Receiver Section & Simulation.mp4 18.6 MB
- ~Get Your Files Here !/3. Section_3 Project with System Generator/5. (Optional) Section_3 Lab 32 Demo JTAG Implementation on Spartan 3E from Sys Gen.mp4 11.1 MB
- ~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/hdl_coder_lms/original_speech.wav 4.0 MB
- ~Get Your Files Here !/4. Section_4 Advance Design with HDL Coder/Section-4-Advance-Design-with-HDL-Coder-with-installation-V2.pdf 3.2 MB
- ~Get Your Files Here !/2. Section_2 Introduction to HDL Coder and System Generator/Section-2-V2-Introduction-to-HDL-Coder-and-System-Generator.pdf 2.0 MB
- ~Get Your Files Here !/3. Section_3 Project with System Generator/Section-3-Basic-Project-with-System-Genrator-V2.pdf 1.3 MB
- ~Get Your Files Here !/1. Section_1 Installation of MatlabSimulink and VIVADOISE/Section-1-V2-Installing-Tools-Matlab-Simulink-and-ISE-VIVADO.pdf 1.1 MB
- Hardware - Frame/Crab Grab (White case).gnw 3.3 MB
- Hardware - Frame/Crab Grab.gnw 3.3 MB
- Hardware - Frame/Donkey Kong II.gnw 3.3 MB
- Hardware - Frame/Donkey Kong Jr. (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Donkey Kong.gnw 3.3 MB
- Hardware - Frame/Fire Attack (Bandits).gnw 3.3 MB
- Hardware - Frame/Fire Attack.gnw 3.3 MB
- Hardware - Frame/Green House.gnw 3.3 MB
- Hardware - Frame/Life Boat.gnw 3.3 MB
- Hardware - Frame/Manhole (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Mario Bros..gnw 3.3 MB
- Hardware - Frame/Mario's Cement Factory (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Mickey & Donald.gnw 3.3 MB
- Hardware - Frame/Oil Panic.gnw 3.3 MB
- Hardware - Frame/Rain Shower.gnw 3.3 MB
- Hardware - Frame/Snoopy Tennis.gnw 3.3 MB
- Hardware - Frame/Spitball Sparky (White case).gnw 3.3 MB
- Hardware - Frame/Spitball Sparky.gnw 3.3 MB
- Hardware - Frame/Squish.gnw 3.3 MB
- Hardware - Frame/Tropical Fish.gnw 3.3 MB
- [ FreeCourseWeb.com ] Udemy - FPGA Image Processing.zip 1.9 GB
- TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD1.bin 684.1 MB
- TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD1.cue 114 Bytes
- TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD2.bin 767.6 MB
- TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE-CD2.cue 114 Bytes
- TLF-SOFT-NI.LabVIEW.v8.6.FPGA.Module.ISO-TBE.nfo 11.7 kB
- Hardware - Frame/Crab Grab (White case).gnw 3.3 MB
- Hardware - Frame/Crab Grab.gnw 3.3 MB
- Hardware - Frame/Donkey Kong II.gnw 3.3 MB
- Hardware - Frame/Donkey Kong Jr. (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Donkey Kong.gnw 3.3 MB
- Hardware - Frame/Fire Attack (Bandits).gnw 3.3 MB
- Hardware - Frame/Fire Attack.gnw 3.3 MB
- Hardware - Frame/Green House.gnw 3.3 MB
- Hardware - Frame/Life Boat.gnw 3.3 MB
- Hardware - Frame/Manhole (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Mario Bros..gnw 3.3 MB
- Hardware - Frame/Mario's Cement Factory (New Wide Screen).gnw 3.3 MB
- Hardware - Frame/Mickey & Donald.gnw 3.3 MB
- Hardware - Frame/Oil Panic.gnw 3.3 MB
- Hardware - Frame/Rain Shower.gnw 3.3 MB
- Hardware - Frame/Snoopy Tennis.gnw 3.3 MB
- Hardware - Frame/Spitball Sparky (White case).gnw 3.3 MB
- Hardware - Frame/Spitball Sparky.gnw 3.3 MB
- Hardware - Frame/Squish.gnw 3.3 MB
- Hardware - Frame/Tropical Fish.gnw 3.3 MB
- 5 - 4._Implementation/27. Xilinx_hardware_demo.mp4 22.6 MB
- 5 - 4._Implementation/26. Xilinx_implementation_demo.mp4 22.0 MB
- 5 - 4._Implementation/23. Intel_implementation_demo.mp4 13.9 MB
- 4 - 3._Hardware_Description_Languages/19. 4-bit_adder_simulation_example.mp4 13.1 MB
- 4 - 3._Hardware_Description_Languages/20. Sequential_logic_simulation_example.mp4 12.3 MB
- 5 - 4._Implementation/24. Intel_hardware_demo.mp4 12.3 MB
- 3 - 2._Embedded_Development_Process/09. FPGA_development_process_overview.mp4 9.8 MB
- 1 - Introduction/01. Get_your_digital_design_journey_started.mp4 9.0 MB
- 4 - 3._Hardware_Description_Languages/16. Verilog_primer.mp4 8.8 MB
- 3 - 2._Embedded_Development_Process/10. FPGA_families_and_development_boards.mp4 8.2 MB
- 2 - 1._Field_Programmable_Gate_Arrays/08. Other_blocks.mp4 7.8 MB
- 2 - 1._Field_Programmable_Gate_Arrays/06. Inside_an_FPGA_-_Logic_blocks.mp4 7.6 MB
- 4 - 3._Hardware_Description_Languages/15. Verilog_and_VHDL.mp4 7.1 MB
- 4 - 3._Hardware_Description_Languages/14. Digital_system_modeling.mp4 6.6 MB
- Ex_Files_FPGA_Development.zip 5.6 MB
- 5 - 4._Implementation/25. Demo_system_for_the_Xilinx_platform.mp4 5.0 MB
- 5 - 4._Implementation/22. Demo_system_for_the_Intel_platform.mp4 4.4 MB
- 3 - 2._Embedded_Development_Process/11. Electronic_design_automation_tools.mp4 3.8 MB
- 2 - 1._Field_Programmable_Gate_Arrays/07. Inside_an_FPGA_-_Interconnects.mp4 3.4 MB
- 5 - 4._Implementation/21. FPGA_example_implementation_requirements.mp4 3.2 MB
- Haskell R. Digital Design Using Digilent FPGA Boards...2010.pdf 160.3 MB
- Wakerly J. Digital Design. Principles and Practices 4ed 2006.pdf 111.1 MB
- Haskell R. Learning By Example Using VHDL...2009.pdf 84.2 MB
- Harris S. Digital Design and Computer Architecture ARM Ed 2016.pdf 35.9 MB
- Harris S. Digital Design and Computer Architecture 2ed 2013.pdf 25.9 MB
- Harris D. Digital Design and Computer Architecture. RISC-V Ed 2022.pdf 24.5 MB
- Mano M. Digital Design With an Introduction to the VHDL 6ed 2017.pdf 23.6 MB
- Mano M. Digital Design With an Introduction to the VHDL 6ed 2019.pdf 20.4 MB
- Wakerly J. Digital Design. Principles and Practices 5ed 2018.pdf 19.9 MB
- Mano M. Digital Design With an Introduction to the VHDL 5ed 2013.pdf 3.1 MB
- Readme.txt 836 Bytes
- [ CourseBoat.com ] Udemy - Video Processing with FPGA.zip 2.8 GB
- 07_design-flows/02_xilinx-partial-reconfiguration-design-flows/05_moudle-based-vs-partial-reconfiguration-design-flows.mp4 93.3 MB
- 04_examples-on-how-to-configure-an-fpga/01_an-example-on-how-to-configure-a-clb/01_4-inputs-1-output-or-lut-configuration-example.mp4 63.8 MB
- 04_examples-on-how-to-configure-an-fpga/01_an-example-on-how-to-configure-a-clb/02_from-the-lut-to-the-clb-configuration-example.mp4 49.7 MB
- 05_an-introduction-to-reconfigurations/04_a-classification-of-reconfigurations/02_a-classification-of-somc-reconfigurations.mp4 42.7 MB
- 05_an-introduction-to-reconfigurations/04_a-classification-of-reconfigurations/01_a-classification-of-soc-reconfigurations.mp4 36.7 MB
- 05_an-introduction-to-reconfigurations/02_the-5-w-s/01_the-5-w-s.mp4 28.1 MB
- 01_a-birds-eye-view-on-adaptive-computing-systems/03_adaptive-computing-systems/05_programmable-system-on-multiple-chip.mp4 27.4 MB
- 03_reconfigurable-computing-and-fpgas/01_getting-familiar-with-fpgas/03_fpga-basic-block-interconnections.mp4 24.2 MB
- 03_reconfigurable-computing-and-fpgas/02_on-how-to-configure-an-fpga/04_configuration-registers.mp4 23.3 MB
- 03_reconfigurable-computing-and-fpgas/01_getting-familiar-with-fpgas/02_fpga-basic-block-clbs-and-iobs.mp4 23.3 MB
- 07_design-flows/02_xilinx-partial-reconfiguration-design-flows/02_xilinx-difference-based-partial-reconfiguration.mp4 22.3 MB
- 01_a-birds-eye-view-on-adaptive-computing-systems/02_fpga-and-reconfiguration/01_fpga-and-reconfiguration-a-1st-definition.mp4 21.9 MB
- 05_an-introduction-to-reconfigurations/01_a-common-vocabulary/01_a-common-vocabulary.mp4 21.1 MB
- 01_a-birds-eye-view-on-adaptive-computing-systems/01_class-intro/03_the-needs-for-adaptation-an-overview.mp4 20.5 MB
- 07_design-flows/01_xilnx-design-flows-through-years/01_xilnx-design-flows-through-years.mp4 20.4 MB
- 07_design-flows/02_xilinx-partial-reconfiguration-design-flows/03_xilinx-module-based-partial-reconfiguration.mp4 20.2 MB
- 07_design-flows/02_xilinx-partial-reconfiguration-design-flows/04_xilinx-partial-reconfiguration-pr-flow.mp4 20.0 MB
- 07_design-flows/02_xilinx-partial-reconfiguration-design-flows/01_partial-reconfiguration-design-flows.mp4 20.0 MB
- 01_a-birds-eye-view-on-adaptive-computing-systems/03_adaptive-computing-systems/04_programmable-system-on-chip.mp4 18.1 MB
- 02_an-introduction-to-reconfigurable-computing/01_reconfigurable-computing/04_fpga-based-reconfigurable-computing.mp4 15.6 MB