verilog -移花宫 -武林禁地，闲人禁止入内

Поляков А. К. - Языки VHDL и VERILOG в проектировании цифровой аппаратуры (Системы проектирования) - 2016.pdf

Поляков А. К. - Языки VHDL и VERILOG в проектировании цифровой аппаратуры (Системы проектирования) - 2016.pdf 40.1 MB

[磁力链接] 添加时间:2023-12-23 大小:40.1 MB 最近下载:2024-11-13 热度:5510

LaMeres B. Quick Start Guide to Verilog 2ed 2023

LaMeres B. Quick Start Guide to Verilog 2ed 2023.pdf 176.6 MB
LaMeres B. Embedded Systems Design using the MSP430FR2355 LaunchPad 2ed 2023.pdf 59.2 MB

[磁力链接] 添加时间:2023-12-31 大小:235.8 MB 最近下载:2024-11-13 热度:1367

Rafiquzzaman M. Digital Logic.Verilog and FPGA-Based Design 2019

Rafiquzzaman M. Digital Logic.Verilog and FPGA-Based Design 2019.pdf 58.2 MB

[磁力链接] 添加时间:2024-01-08 大小:58.2 MB 最近下载:2024-11-08 热度:1722

[ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming

~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench.mp4 557.2 MB
~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench.mp4 342.1 MB
~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB.mp4 263.6 MB
~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator.mp4 97.7 MB
~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART.mp4 31.3 MB
~Get Your Files Here !/01 - Introduction/001 Preview.mp4 28.4 MB
~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication.mp4 25.4 MB
~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment.mp4 23.2 MB
~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator.mp4 12.3 MB
~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART.mp4 10.9 MB
~Get Your Files Here !/02 - Introduction to UART/001 What is UART.mp4 7.2 MB
~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter.mp4 7.0 MB
~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication.mp4 6.5 MB
~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication.mp4 6.1 MB
~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver.mp4 5.8 MB
~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART.mp4 3.5 MB
~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt 46.7 kB
~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt 28.9 kB
~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt 26.5 kB
~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator_en.vtt 10.5 kB

[磁力链接] 添加时间:2024-01-13 大小:1.4 GB 最近下载:2024-11-09 热度:1513

[ DevCourseWeb.com ] Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog

~Get Your Files Here !/3 - I2C/74 - I2C Master without clock stretch.mp4 193.7 MB
~Get Your Files Here !/1 - UART/15 - UART 16550 TX LCR Line Control Register.mp4 94.3 MB
~Get Your Files Here !/1 - UART/26 - UART 16550 Registers THR and RBR.mp4 92.8 MB
~Get Your Files Here !/3 - I2C/78 - I2C Slave without clock stretch.mp4 91.9 MB
~Get Your Files Here !/1 - UART/1 - Simple UART TX.mp4 84.0 MB
~Get Your Files Here !/2 - SPI/47 - Understanding CPOL behavior.mp4 79.5 MB
~Get Your Files Here !/1 - UART/21 - UART 16550 RX RX Logic.mp4 76.4 MB
~Get Your Files Here !/2 - SPI/57 - Digilent PMOD DA4 Analog Devices AD5628 Understanding Specifications.mp4 66.6 MB
~Get Your Files Here !/1 - UART/34 - TX testbench.mp4 65.9 MB
~Get Your Files Here !/3 - I2C/82 - Bit Banging.mp4 59.0 MB
~Get Your Files Here !/1 - UART/17 - UART 16550 TX TX Logic.mp4 52.1 MB
~Get Your Files Here !/3 - I2C/79 - Testbench for top.mp4 51.7 MB
~Get Your Files Here !/1 - UART/14 - TUART 16550 TX Understanding Oversampling in Baud Generator.mp4 50.1 MB
~Get Your Files Here !/1 - UART/16 - UART 16550 TX Stop bits.mp4 49.2 MB
~Get Your Files Here !/1 - UART/29 - UART 16550 Registers LSR.mp4 47.9 MB
~Get Your Files Here !/1 - UART/22 - UART 16550 RX RX TB.mp4 47.9 MB
~Get Your Files Here !/1 - UART/18 - UART 16550 TX TX TB.mp4 47.0 MB
~Get Your Files Here !/1 - UART/28 - UART 16550 Registers FCR and LCR.mp4 46.3 MB
~Get Your Files Here !/1 - UART/3 - Simple UART TB.mp4 43.0 MB
~Get Your Files Here !/1 - UART/8 - UART 16550 FIFO P2.mp4 42.7 MB

[磁力链接] 添加时间:2024-01-27 大小:2.3 GB 最近下载:2024-11-07 热度:1346

[ DevCourseWeb.com ] Udemy - Simple Axi Bus Design Using Verilog Hdl

~Get Your Files Here !/4 - Source code/14 - Design of AXI bus using verilog HDL write process.mp4 292.9 MB
~Get Your Files Here !/4 - Source code/15 - Design of AXI bus using verilog HDL Read process.mp4 129.3 MB
~Get Your Files Here !/1 - Course Introduction/1 - Introduction.mp4 23.6 MB
~Get Your Files Here !/2 - AXI bus/8 - Signal Diagram.mp4 20.9 MB
~Get Your Files Here !/4 - Source code/17 - Test bench simulation.mp4 19.9 MB
~Get Your Files Here !/2 - AXI bus/5 - AXI channel Architecture of Readwrites.mp4 18.4 MB
~Get Your Files Here !/2 - AXI bus/10 - Read process Timing diagram.mp4 15.8 MB
~Get Your Files Here !/1 - Course Introduction/3 - Comparision between AHB AXI APB.mp4 13.5 MB
~Get Your Files Here !/4 - Source code/16 - AXI master slave.mp4 13.4 MB
~Get Your Files Here !/2 - AXI bus/9 - Write process Timing diagram.mp4 12.7 MB
~Get Your Files Here !/2 - AXI bus/6 - AXI signals.mp4 12.6 MB
~Get Your Files Here !/2 - AXI bus/7 - Handshaking signals.mp4 12.5 MB
~Get Your Files Here !/3 - Implementation of Simple AXI bus/13 - AXI MasterSlave Block diagram and Writeread process.mp4 11.6 MB
~Get Your Files Here !/2 - AXI bus/11 - Dependencies between channel handshake signals.mp4 11.5 MB
~Get Your Files Here !/1 - Course Introduction/2 - AMBA introduction.mp4 6.6 MB
~Get Your Files Here !/2 - AXI bus/4 - Introduction to AXI.mp4 6.4 MB
~Get Your Files Here !/3 - Implementation of Simple AXI bus/12 - AXI state machine for write read.mp4 2.5 MB
~Get Your Files Here !/4 - Source code/14 - axi-master-write.v 3.2 kB
~Get Your Files Here !/4 - Source code/14 - axi-slave-write.v 2.7 kB
~Get Your Files Here !/4 - Source code/15 - axi-master-read.v 2.6 kB

[磁力链接] 添加时间:2024-02-15 大小:624.1 MB 最近下载:2024-11-11 热度:1011

[ CourseLala.com ] Introduction to Logic Circuits & Logic Design with Verilog, 2nd edition

~Get Your Files Here !/IntroLogicCircuitsLogic.pdf 42.2 MB
~Get Your Files Here !/Bonus Resources.txt 386 Bytes
Get Bonus Downloads Here.url 180 Bytes

[磁力链接] 添加时间:2024-04-23 大小:42.2 MB 最近下载:2024-11-13 热度:478

Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.djvu

Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.djvu 64.3 MB

[磁力链接] 添加时间:2024-06-28 大小:64.3 MB 最近下载:2024-11-12 热度:3451

Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.pdf

Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.pdf 58.0 MB

[磁力链接] 添加时间:2024-07-05 大小:58.0 MB 最近下载:2024-11-10 热度:1531

[ DevCourseWeb.com ] Udemy - RTL Finite State Machines in System Verilog

~Get Your Files Here !/5 - RTL FSM - Fewer States/3 -Fewer States.mp4 33.9 MB
~Get Your Files Here !/5 - RTL FSM - Fewer States/1 -Measure Latency - 1.mp4 32.8 MB
~Get Your Files Here !/4 - RTL FSM Example/6 -Synthesis.mp4 29.3 MB
~Get Your Files Here !/9 - EDA Playground Setup (Optional)/1 -EDA Playground Hints (Optional).mp4 27.6 MB
~Get Your Files Here !/5 - RTL FSM - Fewer States/2 -Measure Latency - 2.mp4 27.3 MB
~Get Your Files Here !/6 - Extra Explicit One Hot Encoding/2 -GCDOne Hot Encoded.mp4 26.7 MB
~Get Your Files Here !/4 - RTL FSM Example/5 -RTL Simulation - 2.mp4 24.8 MB
~Get Your Files Here !/4 - RTL FSM Example/2 -State Definitions.mp4 21.9 MB
~Get Your Files Here !/4 - RTL FSM Example/4 -RTL Simulation - 1.mp4 20.1 MB
~Get Your Files Here !/4 - RTL FSM Example/3 -Transition Arcs.mp4 17.7 MB
~Get Your Files Here !/8 - Docker Setup (Optional)/1 -Docker Windows Install (Optional).mp4 14.7 MB
~Get Your Files Here !/7 - Wrap Up/1 -Wrap Up.mp4 14.0 MB
~Get Your Files Here !/6 - Extra Explicit One Hot Encoding/5 -Gatesim.mp4 13.6 MB
~Get Your Files Here !/1 - Welcome to the course !/3 -FSMs in Digital Logic.mp4 11.9 MB
~Get Your Files Here !/1 - Welcome to the course !/1 -Introduction.mp4 10.7 MB
~Get Your Files Here !/5 - RTL FSM - Fewer States/4 -Synthesis.mp4 10.2 MB
~Get Your Files Here !/3 - RTL FSM Design Pattern/1 -RTL FSM Design Pattern.mp4 9.2 MB
~Get Your Files Here !/6 - Extra Explicit One Hot Encoding/1 -One-Hot Encoding.mp4 9.0 MB
~Get Your Files Here !/8 - Docker Setup (Optional)/4 -Test Install.mp4 8.0 MB
~Get Your Files Here !/8 - Docker Setup (Optional)/2 -Download Docker Image.mp4 7.5 MB

[磁力链接] 添加时间:2024-10-27 大小:401.2 MB 最近下载:2024-11-11 热度:158