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HDL Books - VHDL FPGA CPLD Verilog Digital Electronics eBook
0131972553 - (2005) Digital Fundamentals.pdf
492.0 MB
0126912955 - (2000) Engineering Digital Design.pdf
50.6 MB
0792397460 - (1996) LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS.pdf
41.7 MB
0965193438 - (1996) HDL Chip Design- A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog.pdf
40.6 MB
0471720925 - (2006) RTL Hardware Design Using VHDL Coding for Efficiency, Portability, and Scalability.pdf
35.8 MB
0072460857 - (2005) Fundamentals of Digital Logic with VHDL Design.pdf
35.6 MB
0132543036 - (2011) Digital Electronics - A Practical Approach with VHDL - 9th Edition.pdf
33.6 MB
0470828498 - (2011) Design for Embedded Image Processing on FPGAs.pdf
28.7 MB
0070471649 - (1999) Verilog Digital System Design.pdf
28.3 MB
0134516753 - (1996) Verilog HDL A Guide to Digital Design and Synthesis B.pdf
22.4 MB
0470185317 - (2008) FPGA Prototyping by VHDL Examples - Xilinx Spartan-3 Version.pdf
22.3 MB
0131543180 - (2005) Practical FPGA Programming in C.chm
18.2 MB
1402055293 - (2007) Processor Design System-On-Chip Computing for ASICs and FPGAs.pdf
15.6 MB
0387284850 - (2006) FPGA Implementations of neural networks.pdf
14.7 MB
0136507638 - (1996) VHDL Made Easy.pdf
13.8 MB
0412616505 - (1997) VHDL A logic synthesis approach.pdf
13.4 MB
1934404055 - (2007) Digital Circuit Analysis and Design with Simulink Modeling and Introduction to CPLDs and FPGAs 2nd Ed.pdf
13.4 MB
0077221435 - (2008) Fundamentals of Digital Logic with VHDL Design - Ed. 3.pdf
12.8 MB
0792395980 - (1995) VHDL Coding Styles and Methodologies.pdf
12.7 MB
0123744385 - (2009) Low-Power Design of Nanometer FPGAs Architecture and EDA.pdf
12.6 MB
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添加时间:
2017-02-25
大小:
1.2 GB
最近下载:
2024-11-30
热度:
6869
Основы языка проектирования цифровой аппаратуры Verilog 2014.pdf
Основы языка проектирования цифровой аппаратуры Verilog 2014.pdf
91.0 MB
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添加时间:
2017-02-09
大小:
91.0 MB
最近下载:
2024-12-01
热度:
6250
Поляков А. К. - Языки VHDL и VERILOG в проектировании цифровой аппаратуры (Системы проектирования) - 2016.pdf
Поляков А. К. - Языки VHDL и VERILOG в проектировании цифровой аппаратуры (Системы проектирования) - 2016.pdf
40.1 MB
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添加时间:
2023-12-23
大小:
40.1 MB
最近下载:
2024-11-30
热度:
5650
[ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification
~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.mp4
118.4 MB
~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.mp4
114.0 MB
~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).mp4
108.0 MB
~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.mp4
81.8 MB
~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).mp4
73.4 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.mp4
62.3 MB
~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.mp4
53.5 MB
~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).mp4
53.3 MB
~Get Your Files Here !/1. Introduction/2. Course overview.mp4
52.9 MB
~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.mp4
52.3 MB
~Get Your Files Here !/1. Introduction/1. Welcome!.mp4
45.8 MB
~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.mp4
44.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.mp4
41.9 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.mp4
41.7 MB
~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.mp4
40.9 MB
~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.mp4
40.5 MB
~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.mp4
39.5 MB
~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.mp4
39.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.mp4
38.5 MB
~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.mp4
38.0 MB
[磁力链接]
添加时间:
2022-02-11
大小:
3.6 GB
最近下载:
2024-11-30
热度:
5331
[ FreeCourseWeb.com ] Lynda - Learning Verilog for FPGA Development.zip
[ FreeCourseWeb.com ] Lynda - Learning Verilog for FPGA Development.zip
322.3 MB
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添加时间:
2021-04-05
大小:
322.3 MB
最近下载:
2024-11-29
热度:
3559
Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.djvu
Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.djvu
64.3 MB
[磁力链接]
添加时间:
2024-06-28
大小:
64.3 MB
最近下载:
2024-11-28
热度:
3526
[ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 1 - Verilog.zip
[ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 1 - Verilog.zip
413.1 MB
[磁力链接]
添加时间:
2021-03-19
大小:
413.1 MB
最近下载:
2024-12-01
热度:
2774
[ FreeCourseWeb.com ] Udemy - Verilog Programming Basics for Programmable Logic IC Chips.zip
[ FreeCourseWeb.com ] Udemy - Verilog Programming Basics for Programmable Logic IC Chips.zip
451.2 MB
[磁力链接]
添加时间:
2021-05-15
大小:
451.2 MB
最近下载:
2024-11-29
热度:
2489
Verilog
142005158X, 1420051547 Verilog HDL; Digital Design and Modeling [Cavanagh 2007-02-20] {CC1E80D1}.pdf
136.4 MB
1118011031 Embedded SoPC Design with Nios II Processor and Verilog Examples [Chu 2012-04-30] {CF1AF375}.pdf
36.7 MB
0070471649 Verilog Digital System Design [Navabi 1999-07-01] {A5772F01}.pdf
28.3 MB
1461473233 SystemVerilog Assertions and Functional Coverage; Guide to Language, Methodology and Applications [Mehta 2013-08-06] {3CEC3C3D}.pdf
23.6 MB
0470185325 FPGA Prototyping by Verilog Examples; Xilinx Spartan-3 Version [Chu 2008-06-30] {86973101}.pdf
22.5 MB
1439811245 Computer Arithmetic and Verilog HDL Fundamentals [Cavanagh 2009-11-24] {1A3A4C2D}.pdf
16.8 MB
3319047884 Digital VLSI Design with Verilog (2nd ed.) [Williams 2014-06-18] {4D1E11E2}.pdf
15.2 MB
1402058284 Digital VLSI Systems Design; A Design Manual for Implementation of Projects on FPGAs and ASICs using Verilog [Ramachandran 2007-07-11] {3B56B1D8}.pdf
14.1 MB
1402084455 Digital VLSI Design with Verilog [Williams 2008-06-26] {A4E71D7E}.pdf
13.3 MB
0897894731 Verilog and SystemVerilog Gotchas; 101 Common Coding Errors and How to Avoid Them [Sutherland & Mills 1997-05-30] {F8EC167E}.pdf
12.5 MB
1461407141 SystemVerilog for Verification; A Guide to Learning the Testbench Language Features (3rd ed.) [Spear & Tumbush 2012-02-14] {320A344F}.pdf
10.4 MB
0134516753 Verilog HDL; A Guide to Digital Design and Synthesis [Palnitkar 1996-01-15] {C41DCF9A}.pdf
9.2 MB
0792380444 Analog Behavioral Modeling with the Verilog; A Language [FitzPatrick & Miller 1997-10-31] {DE013EA4}.pdf
8.3 MB
1402070896 The Verilog Hardware Description Language (5th ed.) [Thomas & Moorby 2002-06-30] {D68FF787}.pdf
8.1 MB
1420074156 Digital Design and Verilog HDL Fundamentals [Cavanagh 2008-06-17] {5EB3F833}.pdf
7.9 MB
1402080441 The Designer's Guide to Verilog AMS [Kundert & Zinke 2004-05-20] {D7F91E28}.pdf
7.8 MB
111865918X Architectures for Computer Vision; From Algorithm to Chip with Verilog [Jeong 2014-10-13] {D8330158}.pdf
7.6 MB
0792381882 The Complete Verilog Book [Sagdeo 1998-06-30] {4C3BA89B}.pdf
6.9 MB
0073380547, 0071318712 Fundamentals of Digital Logic with Verilog Design (3rd ed.) [Brown & Vranesic 2013-02-12] {FDEBFA2D}.pdf
6.5 MB
0792376722 Verilog Quickstart; A Practical Guide to Simulation and Synthesis in Verilog (3rd ed.) [Lee 2005-05-02] {74148A41}.pdf
6.4 MB
[磁力链接]
添加时间:
2022-05-14
大小:
423.9 MB
最近下载:
2024-11-28
热度:
2067
[ DevCourseWeb.com ] Udemy - Verilog on Intel (Altera) FPGA.zip
[ DevCourseWeb.com ] Udemy - Verilog on Intel (Altera) FPGA.zip
3.1 GB
[磁力链接]
添加时间:
2021-03-14
大小:
3.1 GB
最近下载:
2024-11-29
热度:
1763
Rafiquzzaman M. Digital Logic.Verilog and FPGA-Based Design 2019
Rafiquzzaman M. Digital Logic.Verilog and FPGA-Based Design 2019.pdf
58.2 MB
[磁力链接]
添加时间:
2024-01-08
大小:
58.2 MB
最近下载:
2024-11-30
热度:
1760
Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.pdf
Тарасов И. Е. - ПЛИС Xilinx. Языки описания аппаратуры VHDL и Verilog, САПР, приемы проектирования - 2022.pdf
58.0 MB
[磁力链接]
添加时间:
2024-07-05
大小:
58.0 MB
最近下载:
2024-11-29
热度:
1681
[ TutPig.com ] Udemy - Digital Systems and Logic Design with
verilog
codes
~Get Your Files Here !/3 - K-MAP , SIMPLIFICATION AND MINIMIZATION OF BOOLEAN FUNCTIONS/8 - The MAP method.mp4
98.7 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/6 - Canonical And Standard Form.mp4
91.1 MB
~Get Your Files Here !/3 - K-MAP , SIMPLIFICATION AND MINIMIZATION OF BOOLEAN FUNCTIONS/9 - Four value K-Map.mp4
72.1 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/4 - Basic Theorems and properties of Boolean Algebra.mp4
63.5 MB
~Get Your Files Here !/4 - Combinational logic/14 - Full Adder.mp4
59.3 MB
~Get Your Files Here !/4 - Combinational logic/15 - Full Subtractor.mp4
54.9 MB
~Get Your Files Here !/4 - Combinational logic/16 - Decoder.mp4
49.6 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/5 - Digital Circuits implement using Boolean Functions.mp4
38.6 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/7 - Digital logic Gates(AND,OR,NOT,XOR,XNOR,NOR,NAND).mp4
37.9 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/3 - Two Value Boolean Algebra.mp4
33.6 MB
~Get Your Files Here !/4 - Combinational logic/18 - MUX.mp4
31.3 MB
~Get Your Files Here !/4 - Combinational logic/17 - Encoder.mp4
28.6 MB
~Get Your Files Here !/4 - Combinational logic/13 - Half Adder.mp4
21.7 MB
~Get Your Files Here !/3 - K-MAP , SIMPLIFICATION AND MINIMIZATION OF BOOLEAN FUNCTIONS/10 - Don't Care Conditions.mp4
21.1 MB
~Get Your Files Here !/4 - Combinational logic/11 - Introduction of combinational circuits.mp4
18.8 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/2 - Basic Definitions.mp4
15.9 MB
~Get Your Files Here !/1 - Start Here/1 - Introduction of Digital Systems.mp4
11.7 MB
~Get Your Files Here !/5 - Verilog HDL/21 - Full subtractor
verilog
code.mp4
7.4 MB
~Get Your Files Here !/5 - Verilog HDL/19 - Half adder
verilog
code.mp4
3.8 MB
~Get Your Files Here !/5 - Verilog HDL/23 - Encoder
verilog
code.mp4
2.9 MB
[磁力链接]
添加时间:
2022-05-06
大小:
771.0 MB
最近下载:
2024-11-29
热度:
1647
[ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming
~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench.mp4
557.2 MB
~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench.mp4
342.1 MB
~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB.mp4
263.6 MB
~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator.mp4
97.7 MB
~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART.mp4
31.3 MB
~Get Your Files Here !/01 - Introduction/001 Preview.mp4
28.4 MB
~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication.mp4
25.4 MB
~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment.mp4
23.2 MB
~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator.mp4
12.3 MB
~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART.mp4
10.9 MB
~Get Your Files Here !/02 - Introduction to UART/001 What is UART.mp4
7.2 MB
~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter.mp4
7.0 MB
~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication.mp4
6.5 MB
~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication.mp4
6.1 MB
~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver.mp4
5.8 MB
~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART.mp4
3.5 MB
~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt
46.7 kB
~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt
28.9 kB
~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt
26.5 kB
~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator_en.vtt
10.5 kB
[磁力链接]
添加时间:
2024-01-13
大小:
1.4 GB
最近下载:
2024-11-30
热度:
1533
[ FreeCourseWeb.com ] Udemy - VLSI Digital Design using Verilog and hardware- Handson_temp.zip
[ FreeCourseWeb.com ] Udemy - VLSI Digital Design using Verilog and hardware- Handson_temp.zip
8.6 GB
[磁力链接]
添加时间:
2021-04-19
大小:
8.6 GB
最近下载:
2024-11-30
热度:
1473
Embedded SoPC design with NIOSII processor and Verilog examples
Embedded SoPC design with NIOSII processor and Verilog examples-2010kaiser.pdf
36.7 MB
[磁力链接]
添加时间:
2017-02-19
大小:
36.7 MB
最近下载:
2024-11-19
热度:
1463
[ DevCourseWeb.com ] Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog
~Get Your Files Here !/3 - I2C/74 - I2C Master without clock stretch.mp4
193.7 MB
~Get Your Files Here !/1 - UART/15 - UART 16550 TX LCR Line Control Register.mp4
94.3 MB
~Get Your Files Here !/1 - UART/26 - UART 16550 Registers THR and RBR.mp4
92.8 MB
~Get Your Files Here !/3 - I2C/78 - I2C Slave without clock stretch.mp4
91.9 MB
~Get Your Files Here !/1 - UART/1 - Simple UART TX.mp4
84.0 MB
~Get Your Files Here !/2 - SPI/47 - Understanding CPOL behavior.mp4
79.5 MB
~Get Your Files Here !/1 - UART/21 - UART 16550 RX RX Logic.mp4
76.4 MB
~Get Your Files Here !/2 - SPI/57 - Digilent PMOD DA4 Analog Devices AD5628 Understanding Specifications.mp4
66.6 MB
~Get Your Files Here !/1 - UART/34 - TX testbench.mp4
65.9 MB
~Get Your Files Here !/3 - I2C/82 - Bit Banging.mp4
59.0 MB
~Get Your Files Here !/1 - UART/17 - UART 16550 TX TX Logic.mp4
52.1 MB
~Get Your Files Here !/3 - I2C/79 - Testbench for top.mp4
51.7 MB
~Get Your Files Here !/1 - UART/14 - TUART 16550 TX Understanding Oversampling in Baud Generator.mp4
50.1 MB
~Get Your Files Here !/1 - UART/16 - UART 16550 TX Stop bits.mp4
49.2 MB
~Get Your Files Here !/1 - UART/29 - UART 16550 Registers LSR.mp4
47.9 MB
~Get Your Files Here !/1 - UART/22 - UART 16550 RX RX TB.mp4
47.9 MB
~Get Your Files Here !/1 - UART/18 - UART 16550 TX TX TB.mp4
47.0 MB
~Get Your Files Here !/1 - UART/28 - UART 16550 Registers FCR and LCR.mp4
46.3 MB
~Get Your Files Here !/1 - UART/3 - Simple UART TB.mp4
43.0 MB
~Get Your Files Here !/1 - UART/8 - UART 16550 FIFO P2.mp4
42.7 MB
[磁力链接]
添加时间:
2024-01-27
大小:
2.3 GB
最近下载:
2024-11-30
热度:
1401
LaMeres B. Quick Start Guide to Verilog 2ed 2023
LaMeres B. Quick Start Guide to Verilog 2ed 2023.pdf
176.6 MB
LaMeres B. Embedded Systems Design using the MSP430FR2355 LaunchPad 2ed 2023.pdf
59.2 MB
[磁力链接]
添加时间:
2023-12-31
大小:
235.8 MB
最近下载:
2024-11-29
热度:
1379
[ CourseWikia.com ] Udemy - Verilog HDL Through Examples.zip
[ CourseWikia.com ] Udemy - Verilog HDL Through Examples.zip
1.8 GB
[磁力链接]
添加时间:
2022-04-15
大小:
1.8 GB
最近下载:
2024-11-29
热度:
1201
[ DevCourseWeb.com ] Udemy - Simple Axi Bus Design Using Verilog Hdl
~Get Your Files Here !/4 - Source code/14 - Design of AXI bus using
verilog
HDL write process.mp4
292.9 MB
~Get Your Files Here !/4 - Source code/15 - Design of AXI bus using
verilog
HDL Read process.mp4
129.3 MB
~Get Your Files Here !/1 - Course Introduction/1 - Introduction.mp4
23.6 MB
~Get Your Files Here !/2 - AXI bus/8 - Signal Diagram.mp4
20.9 MB
~Get Your Files Here !/4 - Source code/17 - Test bench simulation.mp4
19.9 MB
~Get Your Files Here !/2 - AXI bus/5 - AXI channel Architecture of Readwrites.mp4
18.4 MB
~Get Your Files Here !/2 - AXI bus/10 - Read process Timing diagram.mp4
15.8 MB
~Get Your Files Here !/1 - Course Introduction/3 - Comparision between AHB AXI APB.mp4
13.5 MB
~Get Your Files Here !/4 - Source code/16 - AXI master slave.mp4
13.4 MB
~Get Your Files Here !/2 - AXI bus/9 - Write process Timing diagram.mp4
12.7 MB
~Get Your Files Here !/2 - AXI bus/6 - AXI signals.mp4
12.6 MB
~Get Your Files Here !/2 - AXI bus/7 - Handshaking signals.mp4
12.5 MB
~Get Your Files Here !/3 - Implementation of Simple AXI bus/13 - AXI MasterSlave Block diagram and Writeread process.mp4
11.6 MB
~Get Your Files Here !/2 - AXI bus/11 - Dependencies between channel handshake signals.mp4
11.5 MB
~Get Your Files Here !/1 - Course Introduction/2 - AMBA introduction.mp4
6.6 MB
~Get Your Files Here !/2 - AXI bus/4 - Introduction to AXI.mp4
6.4 MB
~Get Your Files Here !/3 - Implementation of Simple AXI bus/12 - AXI state machine for write read.mp4
2.5 MB
~Get Your Files Here !/4 - Source code/14 - axi-master-write.v
3.2 kB
~Get Your Files Here !/4 - Source code/14 - axi-slave-write.v
2.7 kB
~Get Your Files Here !/4 - Source code/15 - axi-master-read.v
2.6 kB
[磁力链接]
添加时间:
2024-02-15
大小:
624.1 MB
最近下载:
2024-11-29
热度:
1034
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