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[udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]

  • MyFreeOnlineMovies.co.uk.html 189.0 kB
  • Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4 42.2 MB
  • Section 1 Introduction to Vivado/Introduction.mp4 16.9 MB
  • Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4 36.2 MB
  • Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4 48.5 MB
  • Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4 72.5 MB
  • Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4 47.8 MB
  • Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4 53.0 MB
  • Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4 23.3 MB
  • Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4 62.0 MB
  • Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4 21.1 MB
  • Section 4 Lab 3/Learn VHDL by Example.mp4 60.0 MB
  • Section 4 Lab 3/New Text Document.txt 52 Bytes
  • Section 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt 51 Bytes
  • Torrent Downloaded from Glodls.to.txt 237 Bytes
[磁力链接] 添加时间:2017-02-10 大小:483.8 MB 最近下载:2025-08-31 热度:3693

Xilinx Vivado Design Suite 2014.2 ISO-TBE- [MUMBAI-TPB]

  • tbe.nfo 12.1 kB
  • XILINX_Vivado_DS_20142.iso 5.3 GB
  • Follow Me.txt 314 Bytes
[磁力链接] 添加时间:2017-02-20 大小:5.3 GB 最近下载:2025-08-29 热度:2126

Xilinx Vivado Beginners Course to FPGA Development in VHDL

  • Beginners Course to FPGA Development in VHDL.tgz 447.2 MB
  • Torrent downloaded from demonoid.pw.txt 46 Bytes
  • Torrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
[磁力链接] 添加时间:2017-03-26 大小:447.2 MB 最近下载:2025-09-01 热度:2959

Vivado

  • Activation/ise_vivado_petalinux.lic 661 Bytes
  • Activation/licgen_HLS.exe 295.9 kB
  • Activation/Readme.txt 228 Bytes
  • Xilinx_Vivado_SDK_2015.4_1118_2.iso 11.4 GB
[磁力链接] 添加时间:2017-05-09 大小:11.4 GB 最近下载:2025-09-01 热度:2962

vivado videos

  • [MP4 Audio] Discrete Wavelet Transform DWT.mp4 1.6 MB
  • [MP4 480p] Discrete Wavelet Transform DWT.mp4 2.0 MB
  • [MP4 Audio] VHDL#3 - How to simulate VHDL using Vivado.mp4 2.0 MB
  • [MP4 Audio] Using Hardware Co Simulation with Vivado System Generator for DSP.mp4 5.6 MB
  • [MP4 Audio] A Look at MATLAB HDL Coder _ Turning MATLAB Into VHDL.mp4 8.1 MB
  • [MP4 Audio] Getting Started with Vivado High-Level Synthesis.mp4 10.3 MB
  • [MP4 Audio] Working with System Generator for DSP and Platform Design Flows from IP Integrator.mp4 11.7 MB
  • [MP4 1080p] Using Hardware Co Simulation with Vivado System Generator for DSP.mp4 13.5 MB
  • [MP4 1080p] VHDL#3 - How to simulate VHDL using Vivado.mp4 15.1 MB
  • [MP4 Audio] How to Implement discrete wavelet transformation on image by matlab (Encode)【如何使用matlab來實作離散小波轉換】.mp4 18.6 MB
  • [MP4 Audio] Building a Hardware and Software Project _ Targeting the Zynq ZC702 Evaluation Kit.mp4 20.1 MB
  • [MP4 1080p] A Look at MATLAB HDL Coder _ Turning MATLAB Into VHDL.mp4 21.9 MB
  • Xilinx HLS 2 FPGA FIR Filter Design in C in 30 minutes (Vivado High Level Synthesis).mp4 33.1 MB
  • [MP4 Audio] Lecture -20 Discrete Wavelet Transforms.mp4 52.6 MB
  • [MP4 1080p] Working with System Generator for DSP and Platform Design Flows from IP Integrator.mp4 55.5 MB
  • [MP4 480p] How to Implement discrete wavelet transformation on image by matlab (Encode)【如何使用matlab來實作離散小波轉換】.mp4 75.2 MB
  • [MP4 1080p] Getting Started with Vivado High-Level Synthesis.mp4 90.6 MB
  • [MP4 1080p] Building a Hardware and Software Project _ Targeting the Zynq ZC702 Evaluation Kit.mp4 194.9 MB
  • [MP4 480p] Lecture -20 Discrete Wavelet Transforms.mp4 263.4 MB
[磁力链接] 添加时间:2017-07-15 大小:895.9 MB 最近下载:2025-08-19 热度:941

xilinx vivado design suite 2014 2 iso tbe mumbai tpb

  • Follow Me.txt 314 Bytes
  • tbe.nfo 12.1 kB
  • XILINX_Vivado_DS_20142.iso 5.3 GB
[磁力链接] 添加时间:2018-03-24 大小:5.3 GB 最近下载:2021-06-21 热度:5

[ DevCourseWeb.com ] Udemy - VIVADO - Learn From The Beginning! (With PCIe Full Project).zip

  • [ DevCourseWeb.com ] Udemy - VIVADO - Learn From The Beginning! (With PCIe Full Project).zip 4.4 GB
[磁力链接] 添加时间:2021-03-06 大小:4.4 GB 最近下载:2025-09-01 热度:1601

[ FreeCourseWeb.com ] Udemy - Xilinx VIVADO Beginner Course for FPGA Development in VHDL.zip

  • [ FreeCourseWeb.com ] Udemy - Xilinx VIVADO Beginner Course for FPGA Development in VHDL.zip 309.8 MB
[磁力链接] 添加时间:2021-03-19 大小:309.8 MB 最近下载:2025-08-28 热度:1530

[ FreeCourseWeb.com ] Udemy - Getting Started with Xilinx Zynq SoC Devices with Vivado.zip

  • [ FreeCourseWeb.com ] Udemy - Getting Started with Xilinx Zynq SoC Devices with Vivado.zip 3.8 GB
[磁力链接] 添加时间:2021-04-12 大小:3.8 GB 最近下载:2025-09-02 热度:933

[ DevCourseWeb.com ] Udemy - Xilinx Vivado Essentials for the Logic Designer.zip

  • [ DevCourseWeb.com ] Udemy - Xilinx Vivado Essentials for the Logic Designer.zip 1.2 GB
[磁力链接] 添加时间:2022-01-12 大小:1.2 GB 最近下载:2025-08-31 热度:6088

[ FreeCourseWeb.com ] Udemy - Designing a Processor with VHDL and Xilinx Vivado.rar

  • [ FreeCourseWeb.com ] Udemy - Designing a Processor with VHDL and Xilinx Vivado.rar 1.5 GB
[磁力链接] 添加时间:2022-02-10 大小:1.5 GB 最近下载:2025-08-30 热度:2625

vivado 2021.1

  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/petalinux_0002_2021.1_0610_2318.xz 2.2 GB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0571_2021.1_0610_2318.xz 1.7 GB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/data/Third_Party_Software_End_User_License_Agreement.txt 856.6 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0538_2021.1_0610_2318.xz 379.9 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0564_2021.1_0610_2318.xz 369.6 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0708_2021.1_0610_2318.xz 360.5 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0514_2021.1_0610_2318.xz 331.8 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0236_2021.1_0610_2318.xz 330.4 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0765_2021.1_0610_2318.xz 324.3 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0575_2021.1_0610_2318.xz 321.2 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0633_2021.1_0610_2318.xz 309.8 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0025_2021.1_0610_2318.xz 300.3 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0345_2021.1_0610_2318.xz 293.8 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0702_2021.1_0610_2318.xz 291.9 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0678_2021.1_0610_2318.xz 278.3 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0445_2021.1_0610_2318.xz 274.5 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0061_2021.1_0610_2318.xz 272.6 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0353_2021.1_0610_2318.xz 272.1 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0355_2021.1_0610_2318.xz 253.9 MB
  • Xilinx_Unified_2021.1_0610_2318/Xilinx_Unified_2021.1_0610_2318/payload/rdi_0572_2021.1_0610_2318.xz 249.8 MB
[磁力链接] 添加时间:2022-03-18 大小:57.0 GB 最近下载:2025-09-01 热度:11742

[ DevCourseWeb.com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide

  • ~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/005 Step 4 - Add Existing Custom IP.mp4 51.1 MB
  • ~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/001 Project Design Flow Walkthrough.mp4 38.9 MB
  • ~Get Your Files Here !/07 - Automating Vivado/001 TCL Script Introduction.mp4 32.6 MB
  • ~Get Your Files Here !/08 - Hardware Design Debugging and Verification/005 Vivado Debugging Tools Introduction.mp4 32.1 MB
  • ~Get Your Files Here !/10 - High Level Synthesis Tool/001 High Level Synthesis Tool Introduction.mp4 31.0 MB
  • ~Get Your Files Here !/08 - Hardware Design Debugging and Verification/006 How to Use the Integrated Logic Analyzer (ILA) Core for Debugging.mp4 28.3 MB
  • ~Get Your Files Here !/01 - Introduction/001 Welcome to the Course.mp4 26.3 MB
  • ~Get Your Files Here !/08 - Hardware Design Debugging and Verification/007 How to Use the Virtual IO (VIO) Core for Debugging.mp4 24.5 MB
  • ~Get Your Files Here !/01 - Introduction/003 Vivado Download and Installation.mp4 23.2 MB
  • ~Get Your Files Here !/05 - IP Core Design Examples/002 Xilinx Memory Interface Generator (MIG) IP Core.mp4 22.9 MB
  • ~Get Your Files Here !/01 - Introduction/002 Introduction to the Vivado Tool Suite.mp4 22.7 MB
  • ~Get Your Files Here !/04 - Intellectual Property (IP) Cores/004 Create IP Cores from a Block Design.mp4 22.6 MB
  • ~Get Your Files Here !/03 - Pin Planning Tool/001 IO Pin Planning Tool Introduction.mp4 22.0 MB
  • ~Get Your Files Here !/04 - Intellectual Property (IP) Cores/008 Create an AXI IP Core Peripheral Step 3.mp4 22.0 MB
  • ~Get Your Files Here !/04 - Intellectual Property (IP) Cores/003 Create IP Cores from a Specific Directory.mp4 21.2 MB
  • ~Get Your Files Here !/08 - Hardware Design Debugging and Verification/003 Modifying the Simulation Waveform.mp4 20.9 MB
  • ~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/006 Step 5 - Add Create Design Constraints.mp4 20.8 MB
  • ~Get Your Files Here !/02 - Vivado Basics/008 Working with Block Designs in Vivado.mp4 19.8 MB
  • ~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/007 Step 6 - Simulate and Verify Design.mp4 19.6 MB
  • ~Get Your Files Here !/09 - Working with Soft Core Processors/002 Add AXI Peripherals to Your MicroBlaze Processor.mp4 19.1 MB
[磁力链接] 添加时间:2022-05-17 大小:983.5 MB 最近下载:2025-08-22 热度:625

[ DevCourseWeb.com ] Udemy - PYNQ FPGA Development with Python Programming and VIVADO

  • ~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/1. Creating Custom Overlay on PYNQ Addition & Multiplication Application.mp4 197.3 MB
  • ~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/3. Section3_2 Python OpenCV Development with PYNQ FPGA Part I OpenCV Basics.mp4 152.3 MB
  • ~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/1. Machine Learning with Python.mp4 146.8 MB
  • ~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/1. Accelerating Custom Image Processing Function on PYNQ.mp4 145.5 MB
  • ~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/1. Section3_0_Python_Overview.mp4 143.1 MB
  • ~Get Your Files Here !/1. Introduction to PYNQ Architecture/1. PYNQ FPGA Introduction Part I.mp4 130.3 MB
  • ~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/5. Python OpenCV HDMI Streaming & Processing.mp4 129.8 MB
  • ~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/2. Section3_1 Python Programming, Conditional Statements and Loops with PYNQ GPIO.mp4 124.8 MB
  • ~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/4. Section3_2 Python OpenCV Development with PYNQ Part II Face & Eye Detection.mp4 117.7 MB
  • ~Get Your Files Here !/1. Introduction to PYNQ Architecture/3. Section 1 PYNQ Boards & Accessories [Demo].mp4 114.8 MB
  • ~Get Your Files Here !/1. Introduction to PYNQ Architecture/2. PYNQ Introduction Part II.mp4 102.0 MB
  • ~Get Your Files Here !/2. PYNQ Development Methodologies/2. PYNQ FPGA Board Setup & Basic Programming Demo.mp4 101.2 MB
  • ~Get Your Files Here !/2. PYNQ Development Methodologies/1. PYNQ Development Methodologies Overview.mp4 98.9 MB
  • ~Get Your Files Here !/1. Introduction to PYNQ Architecture/4. PYNQ-Z2 Unboxing and Demo [Optional].mp4 97.4 MB
  • ~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/3. Creating PYNQ VDMA Overlay with VIVADO 2021.1 and Python-Notebook.mp4 89.4 MB
  • ~Get Your Files Here !/4. Section 4 Installing Python Library in PYNQ/1. Installing Cryptography Python Library on PYNQ.mp4 55.9 MB
  • ~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/6. PYNQ-License Plate Localizer on Python OpenCV.mp4 42.9 MB
  • ~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/PYNQ_VDMA_Overlay_Sources_HWH_BIT_IPYNB_JPG_S9_2021/vdma/vdma.bit 4.0 MB
  • ~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/project_resizer/resizer.bit 4.0 MB
  • ~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/Char_Recognition_with_PYNQ_V2.ipynb 3.7 MB
[磁力链接] 添加时间:2023-12-18 大小:2.0 GB 最近下载:2025-09-01 热度:3065

[ DevCourseWeb.com ] Udemy - Vivado 2020 - Learn Fpga Development Today!

  • ~Get Your Files Here !/3 - VHDL/13 - Implement your design.mp4 55.5 MB
  • ~Get Your Files Here !/5 - Processor options/20 - Testing and Simulating.mp4 51.6 MB
  • ~Get Your Files Here !/3 - VHDL/12 - Simulating your VHDL code.mp4 48.6 MB
  • ~Get Your Files Here !/5 - Processor options/26 - Generate HDL commands from c based code.mp4 39.2 MB
  • ~Get Your Files Here !/5 - Processor options/24 - Implement a Micro blaze soft Processor.mp4 38.5 MB
  • ~Get Your Files Here !/4 - Memory/19 - Creating a memory block in the integrator.mp4 36.2 MB
  • ~Get Your Files Here !/3 - VHDL/10 - Creating your first project in Vivado.mp4 33.2 MB
  • ~Get Your Files Here !/3 - VHDL/8 - Intro to VHDL.mp4 30.4 MB
  • ~Get Your Files Here !/1 - Introduction/1 - The digital design fundamentals you must learn.mp4 25.8 MB
  • ~Get Your Files Here !/2 - Digital systems/2 - Analog and Digital Systems.mp4 24.2 MB
  • ~Get Your Files Here !/4 - Memory/17 - IP integrator in Vivado.mp4 24.0 MB
  • ~Get Your Files Here !/5 - Processor options/25 - Learn TCL Commands to generate Micro blaze soft processor.mp4 23.8 MB
  • ~Get Your Files Here !/2 - Digital systems/5 - Download and install Vivado.mp4 20.6 MB
  • ~Get Your Files Here !/4 - Memory/16 - IP Flows.mp4 19.6 MB
  • ~Get Your Files Here !/5 - Processor options/23 - Processor Options.mp4 18.3 MB
  • ~Get Your Files Here !/4 - Memory/18 - Memory Controllers.mp4 18.1 MB
  • ~Get Your Files Here !/6 - Conclusion/29 - Conclusion.mp4 18.0 MB
  • ~Get Your Files Here !/3 - VHDL/9 - FPGA Design Flow.mp4 17.2 MB
  • ~Get Your Files Here !/2 - Digital systems/4 - FPGA Architecture.mp4 17.0 MB
  • ~Get Your Files Here !/3 - VHDL/11 - Vivado Design Tools.mp4 16.8 MB
[磁力链接] 添加时间:2023-12-23 大小:669.5 MB 最近下载:2025-09-02 热度:3403

[ WebToolTip.com ] Udemy - FPGA Timings P2 - Clock Domain Crossing(CDC) with Vivado 2024

  • ~Get Your Files Here !/1 - Getting Started with Vivado CDC/11 -False Violations.mp4 43.0 MB
  • ~Get Your Files Here !/2 - Synchronizer/8 -Usage of ASYNC_REG attributes P1.mp4 42.2 MB
  • ~Get Your Files Here !/3 - Single bit CDC/12 -xpm_cdc_single used case P2.mp4 39.8 MB
  • ~Get Your Files Here !/2 - Synchronizer/5 -Synchronizer.mp4 39.8 MB
  • ~Get Your Files Here !/3 - Single bit CDC/6 -Async Reset P3.mp4 38.7 MB
  • ~Get Your Files Here !/2 - Synchronizer/1 -Why combinational output should not be used as input to synchronizer P1.mp4 36.5 MB
  • ~Get Your Files Here !/1 - Getting Started with Vivado CDC/22 -Understanding report_cdc P3.mp4 35.3 MB
  • ~Get Your Files Here !/4 - Multibit CDC/16 -Counter Crossing Manual Approach P7.mp4 34.5 MB
  • ~Get Your Files Here !/2 - Synchronizer/15 -Using Primitives in CDC flow P2.mp4 32.3 MB
  • ~Get Your Files Here !/4 - Multibit CDC/31 -Understanding XPM_CDC_HANDSHAKE P2.mp4 31.2 MB
  • ~Get Your Files Here !/4 - Multibit CDC/32 -Understanding XPM_CDC_HANDSHAKE P3.mp4 30.9 MB
  • ~Get Your Files Here !/1 - Getting Started with Vivado CDC/26 -Understanding report_cdc info P4.mp4 30.3 MB
  • ~Get Your Files Here !/1 - Getting Started with Vivado CDC/23 -Understanding report_cdc info P1.mp4 30.1 MB
  • ~Get Your Files Here !/3 - Single bit CDC/10 -Understanding xpm_cdc_single.mp4 29.7 MB
  • ~Get Your Files Here !/2 - Synchronizer/2 -Why combinational output should not be used as input to synchronizer P2.mp4 29.3 MB
  • ~Get Your Files Here !/1 - Getting Started with Vivado CDC/7 -Demonstration P2.mp4 29.3 MB
  • ~Get Your Files Here !/5 - MTBF/3 -Understanding MTBF & Improving strategies P3.mp4 29.1 MB
  • ~Get Your Files Here !/4 - Multibit CDC/28 -Understanding xpm_fifo_async P2.mp4 27.3 MB
  • ~Get Your Files Here !/1 - Getting Started with Vivado CDC/9 -Clock Interaction report P2.mp4 27.2 MB
  • ~Get Your Files Here !/4 - Multibit CDC/30 -Understanding XPM_CDC_HANDSHAKE P1.mp4 26.9 MB
[磁力链接] 添加时间:2025-07-13 大小:1.9 GB 最近下载:2025-09-02 热度:126

xilinx-vivado.docker.tgz

  • xilinx-vivado.docker.tgz 261.8 GB
[磁力链接] 添加时间:2025-07-31 大小:261.8 GB 最近下载:2025-09-01 热度:39


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